From 74f0f29c99d60a7ed805f949ca7ca94b1e3028ee Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Wed, 29 May 2019 10:41:25 +0100 Subject: [PATCH] latch opcode on instruction issue --- src/experiment/compalu.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/experiment/compalu.py b/src/experiment/compalu.py index 446c7e0f..f517f5cc 100644 --- a/src/experiment/compalu.py +++ b/src/experiment/compalu.py @@ -122,7 +122,7 @@ class ComputationUnitNoDelay(Elaboratable): # m.d.comb += self.alu.op.eq(self.oper_i) # create a latch/register for the operand - latchregister(m, self.oper_i, self.alu.op, opc_l.qn) + latchregister(m, self.oper_i, self.alu.op, self.issue_i) # and one for the output from the ALU data_r = Signal(self.rwid, reset_less=True) # Dest register -- 2.30.2