From 74f2ae3f1fcd4f7b735cbe2207ac84f4d70f8cd0 Mon Sep 17 00:00:00 2001 From: Aaron Sawdey Date: Tue, 2 Feb 2021 19:40:56 -0600 Subject: [PATCH] Fix earlier commit missing patch review changes Somehow I lost my fixes based on Segher's review of the p10 logical-logical fusion patch. This commit adds the changes that should have been there before. Bootstrap/regtest passed. gcc/ChangeLog: * config/rs6000/genfusion.pl (gen_2logical): Add missing fixes based on patch review. * config/rs6000/fusion.md: Regenerate file. --- gcc/config/rs6000/fusion.md | 1920 +++++++++++++++++--------------- gcc/config/rs6000/genfusion.pl | 17 +- 2 files changed, 1033 insertions(+), 904 deletions(-) diff --git a/gcc/config/rs6000/fusion.md b/gcc/config/rs6000/fusion.md index 1ddbe7fe3d2..737a6da385f 100644 --- a/gcc/config/rs6000/fusion.md +++ b/gcc/config/rs6000/fusion.md @@ -357,2176 +357,2304 @@ ;; logical-logical fusion pattern generated by gen_2logical -;; kind: scalar outer: and op and rtl and inv 0 comp 0 -;; inner: and op and rtl and inv 0 comp 0 +;; scalar and -> and (define_insn "*fuse_and_and" - [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r") - (and:GPR (and:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") (match_operand:GPR 1 "gpc_reg_operand" "%r,r,r,r")) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) - (clobber (match_scratch:GPR 4 "=X,X,X,r"))] + [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") + (and:GPR (and:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") + (match_operand:GPR 1 "gpc_reg_operand" "%r,r,r,r")) + (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) + (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ and %3,%1,%0\;and %3,%3,%2 - and %0,%1,%0\;and %0,%0,%2 - and %1,%1,%0\;and %1,%1,%2 + and %3,%1,%0\;and %3,%3,%2 + and %3,%1,%0\;and %3,%3,%2 and %4,%1,%0\;and %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: scalar outer: and op and rtl and inv 0 comp 0 -;; inner: andc op andc rtl and inv 0 comp 1 +;; scalar andc -> and (define_insn "*fuse_andc_and" - [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r") - (and:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) - (clobber (match_scratch:GPR 4 "=X,X,X,r"))] + [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") + (and:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) + (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) + (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) + (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ andc %3,%1,%0\;and %3,%3,%2 - andc %0,%1,%0\;and %0,%0,%2 - andc %1,%1,%0\;and %1,%1,%2 + andc %3,%1,%0\;and %3,%3,%2 + andc %3,%1,%0\;and %3,%3,%2 andc %4,%1,%0\;and %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: scalar outer: and op and rtl and inv 0 comp 0 -;; inner: eqv op eqv rtl xor inv 1 comp 0 +;; scalar eqv -> and (define_insn "*fuse_eqv_and" - [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r") - (and:GPR (not:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) - (clobber (match_scratch:GPR 4 "=X,X,X,r"))] + [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") + (and:GPR (not:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") + (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) + (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) + (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ eqv %3,%1,%0\;and %3,%3,%2 - eqv %0,%1,%0\;and %0,%0,%2 - eqv %1,%1,%0\;and %1,%1,%2 + eqv %3,%1,%0\;and %3,%3,%2 + eqv %3,%1,%0\;and %3,%3,%2 eqv %4,%1,%0\;and %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: scalar outer: and op and rtl and inv 0 comp 0 -;; inner: nand op nand rtl ior inv 0 comp 3 +;; scalar nand -> and (define_insn "*fuse_nand_and" - [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r") - (and:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) - (clobber (match_scratch:GPR 4 "=X,X,X,r"))] + [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") + (and:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) + (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) + (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) + (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ nand %3,%1,%0\;and %3,%3,%2 - nand %0,%1,%0\;and %0,%0,%2 - nand %1,%1,%0\;and %1,%1,%2 + nand %3,%1,%0\;and %3,%3,%2 + nand %3,%1,%0\;and %3,%3,%2 nand %4,%1,%0\;and %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: scalar outer: and op and rtl and inv 0 comp 0 -;; inner: nor op nor rtl and inv 0 comp 3 +;; scalar nor -> and (define_insn "*fuse_nor_and" - [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r") - (and:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) - (clobber (match_scratch:GPR 4 "=X,X,X,r"))] + [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") + (and:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) + (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) + (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) + (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ nor %3,%1,%0\;and %3,%3,%2 - nor %0,%1,%0\;and %0,%0,%2 - nor %1,%1,%0\;and %1,%1,%2 + nor %3,%1,%0\;and %3,%3,%2 + nor %3,%1,%0\;and %3,%3,%2 nor %4,%1,%0\;and %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: scalar outer: and op and rtl and inv 0 comp 0 -;; inner: or op or rtl ior inv 0 comp 0 +;; scalar or -> and (define_insn "*fuse_or_and" - [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r") - (and:GPR (ior:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) - (clobber (match_scratch:GPR 4 "=X,X,X,r"))] + [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") + (and:GPR (ior:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") + (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) + (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) + (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ or %3,%1,%0\;and %3,%3,%2 - or %0,%1,%0\;and %0,%0,%2 - or %1,%1,%0\;and %1,%1,%2 + or %3,%1,%0\;and %3,%3,%2 + or %3,%1,%0\;and %3,%3,%2 or %4,%1,%0\;and %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: scalar outer: and op and rtl and inv 0 comp 0 -;; inner: orc op orc rtl ior inv 0 comp 1 +;; scalar orc -> and (define_insn "*fuse_orc_and" - [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r") - (and:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) - (clobber (match_scratch:GPR 4 "=X,X,X,r"))] + [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") + (and:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) + (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) + (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) + (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ orc %3,%1,%0\;and %3,%3,%2 - orc %0,%1,%0\;and %0,%0,%2 - orc %1,%1,%0\;and %1,%1,%2 + orc %3,%1,%0\;and %3,%3,%2 + orc %3,%1,%0\;and %3,%3,%2 orc %4,%1,%0\;and %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: scalar outer: and op and rtl and inv 0 comp 0 -;; inner: xor op xor rtl xor inv 0 comp 0 +;; scalar xor -> and (define_insn "*fuse_xor_and" - [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r") - (and:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) - (clobber (match_scratch:GPR 4 "=X,X,X,r"))] + [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") + (and:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") + (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) + (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) + (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ xor %3,%1,%0\;and %3,%3,%2 - xor %0,%1,%0\;and %0,%0,%2 - xor %1,%1,%0\;and %1,%1,%2 + xor %3,%1,%0\;and %3,%3,%2 + xor %3,%1,%0\;and %3,%3,%2 xor %4,%1,%0\;and %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: scalar outer: andc op andc rtl and inv 0 comp 1 -;; inner: and op and rtl and inv 0 comp 0 +;; scalar and -> andc (define_insn "*fuse_and_andc" - [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r") - (and:GPR (and:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) - (clobber (match_scratch:GPR 4 "=X,X,X,r"))] + [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") + (and:GPR (and:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") + (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) + (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) + (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ and %3,%1,%0\;andc %3,%3,%2 - and %0,%1,%0\;andc %0,%0,%2 - and %1,%1,%0\;andc %1,%1,%2 + and %3,%1,%0\;andc %3,%3,%2 + and %3,%1,%0\;andc %3,%3,%2 and %4,%1,%0\;andc %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: scalar outer: andc op andc rtl and inv 0 comp 1 -;; inner: andc op andc rtl and inv 0 comp 1 +;; scalar andc -> andc (define_insn "*fuse_andc_andc" - [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r") - (and:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) - (clobber (match_scratch:GPR 4 "=X,X,X,r"))] + [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") + (and:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) + (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) + (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) + (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ andc %3,%1,%0\;andc %3,%3,%2 - andc %0,%1,%0\;andc %0,%0,%2 - andc %1,%1,%0\;andc %1,%1,%2 + andc %3,%1,%0\;andc %3,%3,%2 + andc %3,%1,%0\;andc %3,%3,%2 andc %4,%1,%0\;andc %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: scalar outer: andc op andc rtl and inv 0 comp 1 -;; inner: eqv op eqv rtl xor inv 1 comp 0 +;; scalar eqv -> andc (define_insn "*fuse_eqv_andc" - [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r") - (and:GPR (not:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) - (clobber (match_scratch:GPR 4 "=X,X,X,r"))] + [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") + (and:GPR (not:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") + (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) + (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) + (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ eqv %3,%1,%0\;andc %3,%3,%2 - eqv %0,%1,%0\;andc %0,%0,%2 - eqv %1,%1,%0\;andc %1,%1,%2 + eqv %3,%1,%0\;andc %3,%3,%2 + eqv %3,%1,%0\;andc %3,%3,%2 eqv %4,%1,%0\;andc %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: scalar outer: andc op andc rtl and inv 0 comp 1 -;; inner: nand op nand rtl ior inv 0 comp 3 +;; scalar nand -> andc (define_insn "*fuse_nand_andc" - [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r") - (and:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) - (clobber (match_scratch:GPR 4 "=X,X,X,r"))] + [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") + (and:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) + (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) + (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) + (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ nand %3,%1,%0\;andc %3,%3,%2 - nand %0,%1,%0\;andc %0,%0,%2 - nand %1,%1,%0\;andc %1,%1,%2 + nand %3,%1,%0\;andc %3,%3,%2 + nand %3,%1,%0\;andc %3,%3,%2 nand %4,%1,%0\;andc %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: scalar outer: andc op andc rtl and inv 0 comp 1 -;; inner: nor op nor rtl and inv 0 comp 3 +;; scalar nor -> andc (define_insn "*fuse_nor_andc" - [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r") - (and:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) - (clobber (match_scratch:GPR 4 "=X,X,X,r"))] + [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") + (and:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) + (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) + (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) + (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ nor %3,%1,%0\;andc %3,%3,%2 - nor %0,%1,%0\;andc %0,%0,%2 - nor %1,%1,%0\;andc %1,%1,%2 + nor %3,%1,%0\;andc %3,%3,%2 + nor %3,%1,%0\;andc %3,%3,%2 nor %4,%1,%0\;andc %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: scalar outer: andc op andc rtl and inv 0 comp 1 -;; inner: or op or rtl ior inv 0 comp 0 +;; scalar or -> andc (define_insn "*fuse_or_andc" - [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r") - (and:GPR (ior:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) - (clobber (match_scratch:GPR 4 "=X,X,X,r"))] + [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") + (and:GPR (ior:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") + (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) + (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) + (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ or %3,%1,%0\;andc %3,%3,%2 - or %0,%1,%0\;andc %0,%0,%2 - or %1,%1,%0\;andc %1,%1,%2 + or %3,%1,%0\;andc %3,%3,%2 + or %3,%1,%0\;andc %3,%3,%2 or %4,%1,%0\;andc %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: scalar outer: andc op andc rtl and inv 0 comp 1 -;; inner: orc op orc rtl ior inv 0 comp 1 +;; scalar orc -> andc (define_insn "*fuse_orc_andc" - [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r") - (and:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) - (clobber (match_scratch:GPR 4 "=X,X,X,r"))] + [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") + (and:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) + (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) + (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) + (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ orc %3,%1,%0\;andc %3,%3,%2 - orc %0,%1,%0\;andc %0,%0,%2 - orc %1,%1,%0\;andc %1,%1,%2 + orc %3,%1,%0\;andc %3,%3,%2 + orc %3,%1,%0\;andc %3,%3,%2 orc %4,%1,%0\;andc %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: scalar outer: andc op andc rtl and inv 0 comp 1 -;; inner: xor op xor rtl xor inv 0 comp 0 +;; scalar xor -> andc (define_insn "*fuse_xor_andc" - [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r") - (and:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) - (clobber (match_scratch:GPR 4 "=X,X,X,r"))] + [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") + (and:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") + (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) + (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) + (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ xor %3,%1,%0\;andc %3,%3,%2 - xor %0,%1,%0\;andc %0,%0,%2 - xor %1,%1,%0\;andc %1,%1,%2 + xor %3,%1,%0\;andc %3,%3,%2 + xor %3,%1,%0\;andc %3,%3,%2 xor %4,%1,%0\;andc %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: scalar outer: eqv op eqv rtl xor inv 1 comp 0 -;; inner: and op and rtl and inv 0 comp 0 +;; scalar and -> eqv (define_insn "*fuse_and_eqv" - [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r") - (not:GPR (xor:GPR (and:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) - (clobber (match_scratch:GPR 4 "=X,X,X,r"))] + [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") + (not:GPR (xor:GPR (and:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") + (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) + (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) + (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ and %3,%1,%0\;eqv %3,%3,%2 - and %0,%1,%0\;eqv %0,%0,%2 - and %1,%1,%0\;eqv %1,%1,%2 + and %3,%1,%0\;eqv %3,%3,%2 + and %3,%1,%0\;eqv %3,%3,%2 and %4,%1,%0\;eqv %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: scalar outer: eqv op eqv rtl xor inv 1 comp 0 -;; inner: andc op andc rtl and inv 0 comp 1 +;; scalar andc -> eqv (define_insn "*fuse_andc_eqv" - [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r") - (not:GPR (xor:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) - (clobber (match_scratch:GPR 4 "=X,X,X,r"))] + [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") + (not:GPR (xor:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) + (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) + (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) + (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ andc %3,%1,%0\;eqv %3,%3,%2 - andc %0,%1,%0\;eqv %0,%0,%2 - andc %1,%1,%0\;eqv %1,%1,%2 + andc %3,%1,%0\;eqv %3,%3,%2 + andc %3,%1,%0\;eqv %3,%3,%2 andc %4,%1,%0\;eqv %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: scalar outer: eqv op eqv rtl xor inv 1 comp 0 -;; inner: eqv op eqv rtl xor inv 1 comp 0 +;; scalar eqv -> eqv (define_insn "*fuse_eqv_eqv" - [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r") - (not:GPR (xor:GPR (not:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") (match_operand:GPR 1 "gpc_reg_operand" "%r,r,r,r"))) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) - (clobber (match_scratch:GPR 4 "=X,X,X,r"))] + [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") + (not:GPR (xor:GPR (not:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") + (match_operand:GPR 1 "gpc_reg_operand" "%r,r,r,r"))) + (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) + (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ eqv %3,%1,%0\;eqv %3,%3,%2 - eqv %0,%1,%0\;eqv %0,%0,%2 - eqv %1,%1,%0\;eqv %1,%1,%2 + eqv %3,%1,%0\;eqv %3,%3,%2 + eqv %3,%1,%0\;eqv %3,%3,%2 eqv %4,%1,%0\;eqv %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: scalar outer: eqv op eqv rtl xor inv 1 comp 0 -;; inner: nand op nand rtl ior inv 0 comp 3 +;; scalar nand -> eqv (define_insn "*fuse_nand_eqv" - [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r") - (not:GPR (xor:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) - (clobber (match_scratch:GPR 4 "=X,X,X,r"))] + [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") + (not:GPR (xor:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) + (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) + (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) + (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ nand %3,%1,%0\;eqv %3,%3,%2 - nand %0,%1,%0\;eqv %0,%0,%2 - nand %1,%1,%0\;eqv %1,%1,%2 + nand %3,%1,%0\;eqv %3,%3,%2 + nand %3,%1,%0\;eqv %3,%3,%2 nand %4,%1,%0\;eqv %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: scalar outer: eqv op eqv rtl xor inv 1 comp 0 -;; inner: nor op nor rtl and inv 0 comp 3 +;; scalar nor -> eqv (define_insn "*fuse_nor_eqv" - [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r") - (not:GPR (xor:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) - (clobber (match_scratch:GPR 4 "=X,X,X,r"))] + [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") + (not:GPR (xor:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) + (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) + (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) + (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ nor %3,%1,%0\;eqv %3,%3,%2 - nor %0,%1,%0\;eqv %0,%0,%2 - nor %1,%1,%0\;eqv %1,%1,%2 + nor %3,%1,%0\;eqv %3,%3,%2 + nor %3,%1,%0\;eqv %3,%3,%2 nor %4,%1,%0\;eqv %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: scalar outer: eqv op eqv rtl xor inv 1 comp 0 -;; inner: or op or rtl ior inv 0 comp 0 +;; scalar or -> eqv (define_insn "*fuse_or_eqv" - [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r") - (not:GPR (xor:GPR (ior:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) - (clobber (match_scratch:GPR 4 "=X,X,X,r"))] + [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") + (not:GPR (xor:GPR (ior:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") + (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) + (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) + (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ or %3,%1,%0\;eqv %3,%3,%2 - or %0,%1,%0\;eqv %0,%0,%2 - or %1,%1,%0\;eqv %1,%1,%2 + or %3,%1,%0\;eqv %3,%3,%2 + or %3,%1,%0\;eqv %3,%3,%2 or %4,%1,%0\;eqv %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: scalar outer: eqv op eqv rtl xor inv 1 comp 0 -;; inner: orc op orc rtl ior inv 0 comp 1 +;; scalar orc -> eqv (define_insn "*fuse_orc_eqv" - [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r") - (not:GPR (xor:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) - (clobber (match_scratch:GPR 4 "=X,X,X,r"))] + [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") + (not:GPR (xor:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) + (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) + (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) + (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ orc %3,%1,%0\;eqv %3,%3,%2 - orc %0,%1,%0\;eqv %0,%0,%2 - orc %1,%1,%0\;eqv %1,%1,%2 + orc %3,%1,%0\;eqv %3,%3,%2 + orc %3,%1,%0\;eqv %3,%3,%2 orc %4,%1,%0\;eqv %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: scalar outer: eqv op eqv rtl xor inv 1 comp 0 -;; inner: xor op xor rtl xor inv 0 comp 0 +;; scalar xor -> eqv (define_insn "*fuse_xor_eqv" - [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r") - (not:GPR (xor:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) - (clobber (match_scratch:GPR 4 "=X,X,X,r"))] + [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") + (not:GPR (xor:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") + (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) + (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) + (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ xor %3,%1,%0\;eqv %3,%3,%2 - xor %0,%1,%0\;eqv %0,%0,%2 - xor %1,%1,%0\;eqv %1,%1,%2 + xor %3,%1,%0\;eqv %3,%3,%2 + xor %3,%1,%0\;eqv %3,%3,%2 xor %4,%1,%0\;eqv %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: scalar outer: nand op nand rtl ior inv 0 comp 3 -;; inner: and op and rtl and inv 0 comp 0 +;; scalar and -> nand (define_insn "*fuse_and_nand" - [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r") - (ior:GPR (not:GPR (and:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) - (clobber (match_scratch:GPR 4 "=X,X,X,r"))] + [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") + (ior:GPR (not:GPR (and:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") + (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) + (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) + (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ and %3,%1,%0\;nand %3,%3,%2 - and %0,%1,%0\;nand %0,%0,%2 - and %1,%1,%0\;nand %1,%1,%2 + and %3,%1,%0\;nand %3,%3,%2 + and %3,%1,%0\;nand %3,%3,%2 and %4,%1,%0\;nand %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: scalar outer: nand op nand rtl ior inv 0 comp 3 -;; inner: andc op andc rtl and inv 0 comp 1 +;; scalar andc -> nand (define_insn "*fuse_andc_nand" - [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r") - (ior:GPR (not:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) - (clobber (match_scratch:GPR 4 "=X,X,X,r"))] + [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") + (ior:GPR (not:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) + (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) + (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) + (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ andc %3,%1,%0\;nand %3,%3,%2 - andc %0,%1,%0\;nand %0,%0,%2 - andc %1,%1,%0\;nand %1,%1,%2 + andc %3,%1,%0\;nand %3,%3,%2 + andc %3,%1,%0\;nand %3,%3,%2 andc %4,%1,%0\;nand %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: scalar outer: nand op nand rtl ior inv 0 comp 3 -;; inner: eqv op eqv rtl xor inv 1 comp 0 +;; scalar eqv -> nand (define_insn "*fuse_eqv_nand" - [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r") - (ior:GPR (not:GPR (not:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")))) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) - (clobber (match_scratch:GPR 4 "=X,X,X,r"))] + [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") + (ior:GPR (not:GPR (not:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") + (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")))) + (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) + (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ eqv %3,%1,%0\;nand %3,%3,%2 - eqv %0,%1,%0\;nand %0,%0,%2 - eqv %1,%1,%0\;nand %1,%1,%2 + eqv %3,%1,%0\;nand %3,%3,%2 + eqv %3,%1,%0\;nand %3,%3,%2 eqv %4,%1,%0\;nand %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: scalar outer: nand op nand rtl ior inv 0 comp 3 -;; inner: nand op nand rtl ior inv 0 comp 3 +;; scalar nand -> nand (define_insn "*fuse_nand_nand" - [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r") - (ior:GPR (not:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")))) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) - (clobber (match_scratch:GPR 4 "=X,X,X,r"))] + [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") + (ior:GPR (not:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) + (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")))) + (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) + (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ nand %3,%1,%0\;nand %3,%3,%2 - nand %0,%1,%0\;nand %0,%0,%2 - nand %1,%1,%0\;nand %1,%1,%2 + nand %3,%1,%0\;nand %3,%3,%2 + nand %3,%1,%0\;nand %3,%3,%2 nand %4,%1,%0\;nand %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: scalar outer: nand op nand rtl ior inv 0 comp 3 -;; inner: nor op nor rtl and inv 0 comp 3 +;; scalar nor -> nand (define_insn "*fuse_nor_nand" - [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r") - (ior:GPR (not:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")))) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) - (clobber (match_scratch:GPR 4 "=X,X,X,r"))] + [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") + (ior:GPR (not:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) + (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")))) + (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) + (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ nor %3,%1,%0\;nand %3,%3,%2 - nor %0,%1,%0\;nand %0,%0,%2 - nor %1,%1,%0\;nand %1,%1,%2 + nor %3,%1,%0\;nand %3,%3,%2 + nor %3,%1,%0\;nand %3,%3,%2 nor %4,%1,%0\;nand %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: scalar outer: nand op nand rtl ior inv 0 comp 3 -;; inner: or op or rtl ior inv 0 comp 0 +;; scalar or -> nand (define_insn "*fuse_or_nand" - [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r") - (ior:GPR (not:GPR (ior:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) - (clobber (match_scratch:GPR 4 "=X,X,X,r"))] + [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") + (ior:GPR (not:GPR (ior:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") + (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) + (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) + (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ or %3,%1,%0\;nand %3,%3,%2 - or %0,%1,%0\;nand %0,%0,%2 - or %1,%1,%0\;nand %1,%1,%2 + or %3,%1,%0\;nand %3,%3,%2 + or %3,%1,%0\;nand %3,%3,%2 or %4,%1,%0\;nand %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: scalar outer: nand op nand rtl ior inv 0 comp 3 -;; inner: orc op orc rtl ior inv 0 comp 1 +;; scalar orc -> nand (define_insn "*fuse_orc_nand" - [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r") - (ior:GPR (not:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) - (clobber (match_scratch:GPR 4 "=X,X,X,r"))] + [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") + (ior:GPR (not:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) + (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) + (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) + (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ orc %3,%1,%0\;nand %3,%3,%2 - orc %0,%1,%0\;nand %0,%0,%2 - orc %1,%1,%0\;nand %1,%1,%2 + orc %3,%1,%0\;nand %3,%3,%2 + orc %3,%1,%0\;nand %3,%3,%2 orc %4,%1,%0\;nand %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: scalar outer: nand op nand rtl ior inv 0 comp 3 -;; inner: xor op xor rtl xor inv 0 comp 0 +;; scalar xor -> nand (define_insn "*fuse_xor_nand" - [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r") - (ior:GPR (not:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) - (clobber (match_scratch:GPR 4 "=X,X,X,r"))] + [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") + (ior:GPR (not:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") + (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) + (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) + (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ xor %3,%1,%0\;nand %3,%3,%2 - xor %0,%1,%0\;nand %0,%0,%2 - xor %1,%1,%0\;nand %1,%1,%2 + xor %3,%1,%0\;nand %3,%3,%2 + xor %3,%1,%0\;nand %3,%3,%2 xor %4,%1,%0\;nand %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: scalar outer: nor op nor rtl and inv 0 comp 3 -;; inner: and op and rtl and inv 0 comp 0 +;; scalar and -> nor (define_insn "*fuse_and_nor" - [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r") - (and:GPR (not:GPR (and:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) - (clobber (match_scratch:GPR 4 "=X,X,X,r"))] + [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") + (and:GPR (not:GPR (and:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") + (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) + (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) + (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ and %3,%1,%0\;nor %3,%3,%2 - and %0,%1,%0\;nor %0,%0,%2 - and %1,%1,%0\;nor %1,%1,%2 + and %3,%1,%0\;nor %3,%3,%2 + and %3,%1,%0\;nor %3,%3,%2 and %4,%1,%0\;nor %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: scalar outer: nor op nor rtl and inv 0 comp 3 -;; inner: andc op andc rtl and inv 0 comp 1 +;; scalar andc -> nor (define_insn "*fuse_andc_nor" - [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r") - (and:GPR (not:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) - (clobber (match_scratch:GPR 4 "=X,X,X,r"))] + [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") + (and:GPR (not:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) + (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) + (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) + (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ andc %3,%1,%0\;nor %3,%3,%2 - andc %0,%1,%0\;nor %0,%0,%2 - andc %1,%1,%0\;nor %1,%1,%2 + andc %3,%1,%0\;nor %3,%3,%2 + andc %3,%1,%0\;nor %3,%3,%2 andc %4,%1,%0\;nor %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: scalar outer: nor op nor rtl and inv 0 comp 3 -;; inner: eqv op eqv rtl xor inv 1 comp 0 +;; scalar eqv -> nor (define_insn "*fuse_eqv_nor" - [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r") - (and:GPR (not:GPR (not:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")))) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) - (clobber (match_scratch:GPR 4 "=X,X,X,r"))] + [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") + (and:GPR (not:GPR (not:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") + (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")))) + (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) + (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ eqv %3,%1,%0\;nor %3,%3,%2 - eqv %0,%1,%0\;nor %0,%0,%2 - eqv %1,%1,%0\;nor %1,%1,%2 + eqv %3,%1,%0\;nor %3,%3,%2 + eqv %3,%1,%0\;nor %3,%3,%2 eqv %4,%1,%0\;nor %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: scalar outer: nor op nor rtl and inv 0 comp 3 -;; inner: nand op nand rtl ior inv 0 comp 3 +;; scalar nand -> nor (define_insn "*fuse_nand_nor" - [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r") - (and:GPR (not:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")))) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) - (clobber (match_scratch:GPR 4 "=X,X,X,r"))] + [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") + (and:GPR (not:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) + (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")))) + (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) + (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ nand %3,%1,%0\;nor %3,%3,%2 - nand %0,%1,%0\;nor %0,%0,%2 - nand %1,%1,%0\;nor %1,%1,%2 + nand %3,%1,%0\;nor %3,%3,%2 + nand %3,%1,%0\;nor %3,%3,%2 nand %4,%1,%0\;nor %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: scalar outer: nor op nor rtl and inv 0 comp 3 -;; inner: nor op nor rtl and inv 0 comp 3 +;; scalar nor -> nor (define_insn "*fuse_nor_nor" - [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r") - (and:GPR (not:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")))) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) - (clobber (match_scratch:GPR 4 "=X,X,X,r"))] + [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") + (and:GPR (not:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) + (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")))) + (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) + (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ nor %3,%1,%0\;nor %3,%3,%2 - nor %0,%1,%0\;nor %0,%0,%2 - nor %1,%1,%0\;nor %1,%1,%2 + nor %3,%1,%0\;nor %3,%3,%2 + nor %3,%1,%0\;nor %3,%3,%2 nor %4,%1,%0\;nor %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: scalar outer: nor op nor rtl and inv 0 comp 3 -;; inner: or op or rtl ior inv 0 comp 0 +;; scalar or -> nor (define_insn "*fuse_or_nor" - [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r") - (and:GPR (not:GPR (ior:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) - (clobber (match_scratch:GPR 4 "=X,X,X,r"))] + [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") + (and:GPR (not:GPR (ior:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") + (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) + (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) + (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ or %3,%1,%0\;nor %3,%3,%2 - or %0,%1,%0\;nor %0,%0,%2 - or %1,%1,%0\;nor %1,%1,%2 + or %3,%1,%0\;nor %3,%3,%2 + or %3,%1,%0\;nor %3,%3,%2 or %4,%1,%0\;nor %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: scalar outer: nor op nor rtl and inv 0 comp 3 -;; inner: orc op orc rtl ior inv 0 comp 1 +;; scalar orc -> nor (define_insn "*fuse_orc_nor" - [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r") - (and:GPR (not:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) - (clobber (match_scratch:GPR 4 "=X,X,X,r"))] + [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") + (and:GPR (not:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) + (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) + (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) + (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ orc %3,%1,%0\;nor %3,%3,%2 - orc %0,%1,%0\;nor %0,%0,%2 - orc %1,%1,%0\;nor %1,%1,%2 + orc %3,%1,%0\;nor %3,%3,%2 + orc %3,%1,%0\;nor %3,%3,%2 orc %4,%1,%0\;nor %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: scalar outer: nor op nor rtl and inv 0 comp 3 -;; inner: xor op xor rtl xor inv 0 comp 0 +;; scalar xor -> nor (define_insn "*fuse_xor_nor" - [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r") - (and:GPR (not:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) - (clobber (match_scratch:GPR 4 "=X,X,X,r"))] + [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") + (and:GPR (not:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") + (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) + (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) + (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ xor %3,%1,%0\;nor %3,%3,%2 - xor %0,%1,%0\;nor %0,%0,%2 - xor %1,%1,%0\;nor %1,%1,%2 + xor %3,%1,%0\;nor %3,%3,%2 + xor %3,%1,%0\;nor %3,%3,%2 xor %4,%1,%0\;nor %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: scalar outer: or op or rtl ior inv 0 comp 0 -;; inner: and op and rtl and inv 0 comp 0 +;; scalar and -> or (define_insn "*fuse_and_or" - [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r") - (ior:GPR (and:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) - (clobber (match_scratch:GPR 4 "=X,X,X,r"))] + [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") + (ior:GPR (and:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") + (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) + (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) + (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ and %3,%1,%0\;or %3,%3,%2 - and %0,%1,%0\;or %0,%0,%2 - and %1,%1,%0\;or %1,%1,%2 + and %3,%1,%0\;or %3,%3,%2 + and %3,%1,%0\;or %3,%3,%2 and %4,%1,%0\;or %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: scalar outer: or op or rtl ior inv 0 comp 0 -;; inner: andc op andc rtl and inv 0 comp 1 +;; scalar andc -> or (define_insn "*fuse_andc_or" - [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r") - (ior:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) - (clobber (match_scratch:GPR 4 "=X,X,X,r"))] + [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") + (ior:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) + (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) + (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) + (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ andc %3,%1,%0\;or %3,%3,%2 - andc %0,%1,%0\;or %0,%0,%2 - andc %1,%1,%0\;or %1,%1,%2 + andc %3,%1,%0\;or %3,%3,%2 + andc %3,%1,%0\;or %3,%3,%2 andc %4,%1,%0\;or %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: scalar outer: or op or rtl ior inv 0 comp 0 -;; inner: eqv op eqv rtl xor inv 1 comp 0 +;; scalar eqv -> or (define_insn "*fuse_eqv_or" - [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r") - (ior:GPR (not:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) - (clobber (match_scratch:GPR 4 "=X,X,X,r"))] + [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") + (ior:GPR (not:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") + (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) + (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) + (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ eqv %3,%1,%0\;or %3,%3,%2 - eqv %0,%1,%0\;or %0,%0,%2 - eqv %1,%1,%0\;or %1,%1,%2 + eqv %3,%1,%0\;or %3,%3,%2 + eqv %3,%1,%0\;or %3,%3,%2 eqv %4,%1,%0\;or %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: scalar outer: or op or rtl ior inv 0 comp 0 -;; inner: nand op nand rtl ior inv 0 comp 3 +;; scalar nand -> or (define_insn "*fuse_nand_or" - [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r") - (ior:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) - (clobber (match_scratch:GPR 4 "=X,X,X,r"))] + [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") + (ior:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) + (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) + (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) + (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ nand %3,%1,%0\;or %3,%3,%2 - nand %0,%1,%0\;or %0,%0,%2 - nand %1,%1,%0\;or %1,%1,%2 + nand %3,%1,%0\;or %3,%3,%2 + nand %3,%1,%0\;or %3,%3,%2 nand %4,%1,%0\;or %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: scalar outer: or op or rtl ior inv 0 comp 0 -;; inner: nor op nor rtl and inv 0 comp 3 +;; scalar nor -> or (define_insn "*fuse_nor_or" - [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r") - (ior:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) - (clobber (match_scratch:GPR 4 "=X,X,X,r"))] + [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") + (ior:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) + (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) + (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) + (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ nor %3,%1,%0\;or %3,%3,%2 - nor %0,%1,%0\;or %0,%0,%2 - nor %1,%1,%0\;or %1,%1,%2 + nor %3,%1,%0\;or %3,%3,%2 + nor %3,%1,%0\;or %3,%3,%2 nor %4,%1,%0\;or %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: scalar outer: or op or rtl ior inv 0 comp 0 -;; inner: or op or rtl ior inv 0 comp 0 +;; scalar or -> or (define_insn "*fuse_or_or" - [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r") - (ior:GPR (ior:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") (match_operand:GPR 1 "gpc_reg_operand" "%r,r,r,r")) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) - (clobber (match_scratch:GPR 4 "=X,X,X,r"))] + [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") + (ior:GPR (ior:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") + (match_operand:GPR 1 "gpc_reg_operand" "%r,r,r,r")) + (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) + (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ or %3,%1,%0\;or %3,%3,%2 - or %0,%1,%0\;or %0,%0,%2 - or %1,%1,%0\;or %1,%1,%2 + or %3,%1,%0\;or %3,%3,%2 + or %3,%1,%0\;or %3,%3,%2 or %4,%1,%0\;or %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: scalar outer: or op or rtl ior inv 0 comp 0 -;; inner: orc op orc rtl ior inv 0 comp 1 +;; scalar orc -> or (define_insn "*fuse_orc_or" - [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r") - (ior:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) - (clobber (match_scratch:GPR 4 "=X,X,X,r"))] + [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") + (ior:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) + (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) + (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) + (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ orc %3,%1,%0\;or %3,%3,%2 - orc %0,%1,%0\;or %0,%0,%2 - orc %1,%1,%0\;or %1,%1,%2 + orc %3,%1,%0\;or %3,%3,%2 + orc %3,%1,%0\;or %3,%3,%2 orc %4,%1,%0\;or %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: scalar outer: or op or rtl ior inv 0 comp 0 -;; inner: xor op xor rtl xor inv 0 comp 0 +;; scalar xor -> or (define_insn "*fuse_xor_or" - [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r") - (ior:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) - (clobber (match_scratch:GPR 4 "=X,X,X,r"))] + [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") + (ior:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") + (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) + (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) + (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ xor %3,%1,%0\;or %3,%3,%2 - xor %0,%1,%0\;or %0,%0,%2 - xor %1,%1,%0\;or %1,%1,%2 + xor %3,%1,%0\;or %3,%3,%2 + xor %3,%1,%0\;or %3,%3,%2 xor %4,%1,%0\;or %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: scalar outer: orc op orc rtl ior inv 0 comp 1 -;; inner: and op and rtl and inv 0 comp 0 +;; scalar and -> orc (define_insn "*fuse_and_orc" - [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r") - (ior:GPR (and:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) - (clobber (match_scratch:GPR 4 "=X,X,X,r"))] + [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") + (ior:GPR (and:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") + (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) + (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) + (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ and %3,%1,%0\;orc %3,%3,%2 - and %0,%1,%0\;orc %0,%0,%2 - and %1,%1,%0\;orc %1,%1,%2 + and %3,%1,%0\;orc %3,%3,%2 + and %3,%1,%0\;orc %3,%3,%2 and %4,%1,%0\;orc %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: scalar outer: orc op orc rtl ior inv 0 comp 1 -;; inner: andc op andc rtl and inv 0 comp 1 +;; scalar andc -> orc (define_insn "*fuse_andc_orc" - [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r") - (ior:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) - (clobber (match_scratch:GPR 4 "=X,X,X,r"))] + [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") + (ior:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) + (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) + (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) + (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ andc %3,%1,%0\;orc %3,%3,%2 - andc %0,%1,%0\;orc %0,%0,%2 - andc %1,%1,%0\;orc %1,%1,%2 + andc %3,%1,%0\;orc %3,%3,%2 + andc %3,%1,%0\;orc %3,%3,%2 andc %4,%1,%0\;orc %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: scalar outer: orc op orc rtl ior inv 0 comp 1 -;; inner: eqv op eqv rtl xor inv 1 comp 0 +;; scalar eqv -> orc (define_insn "*fuse_eqv_orc" - [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r") - (ior:GPR (not:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) - (clobber (match_scratch:GPR 4 "=X,X,X,r"))] + [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") + (ior:GPR (not:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") + (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) + (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) + (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ eqv %3,%1,%0\;orc %3,%3,%2 - eqv %0,%1,%0\;orc %0,%0,%2 - eqv %1,%1,%0\;orc %1,%1,%2 + eqv %3,%1,%0\;orc %3,%3,%2 + eqv %3,%1,%0\;orc %3,%3,%2 eqv %4,%1,%0\;orc %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: scalar outer: orc op orc rtl ior inv 0 comp 1 -;; inner: nand op nand rtl ior inv 0 comp 3 +;; scalar nand -> orc (define_insn "*fuse_nand_orc" - [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r") - (ior:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) - (clobber (match_scratch:GPR 4 "=X,X,X,r"))] + [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") + (ior:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) + (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) + (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) + (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ nand %3,%1,%0\;orc %3,%3,%2 - nand %0,%1,%0\;orc %0,%0,%2 - nand %1,%1,%0\;orc %1,%1,%2 + nand %3,%1,%0\;orc %3,%3,%2 + nand %3,%1,%0\;orc %3,%3,%2 nand %4,%1,%0\;orc %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: scalar outer: orc op orc rtl ior inv 0 comp 1 -;; inner: nor op nor rtl and inv 0 comp 3 +;; scalar nor -> orc (define_insn "*fuse_nor_orc" - [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r") - (ior:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) - (clobber (match_scratch:GPR 4 "=X,X,X,r"))] + [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") + (ior:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) + (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) + (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) + (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ nor %3,%1,%0\;orc %3,%3,%2 - nor %0,%1,%0\;orc %0,%0,%2 - nor %1,%1,%0\;orc %1,%1,%2 + nor %3,%1,%0\;orc %3,%3,%2 + nor %3,%1,%0\;orc %3,%3,%2 nor %4,%1,%0\;orc %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: scalar outer: orc op orc rtl ior inv 0 comp 1 -;; inner: or op or rtl ior inv 0 comp 0 +;; scalar or -> orc (define_insn "*fuse_or_orc" - [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r") - (ior:GPR (ior:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) - (clobber (match_scratch:GPR 4 "=X,X,X,r"))] + [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") + (ior:GPR (ior:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") + (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) + (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) + (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ or %3,%1,%0\;orc %3,%3,%2 - or %0,%1,%0\;orc %0,%0,%2 - or %1,%1,%0\;orc %1,%1,%2 + or %3,%1,%0\;orc %3,%3,%2 + or %3,%1,%0\;orc %3,%3,%2 or %4,%1,%0\;orc %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: scalar outer: orc op orc rtl ior inv 0 comp 1 -;; inner: orc op orc rtl ior inv 0 comp 1 +;; scalar orc -> orc (define_insn "*fuse_orc_orc" - [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r") - (ior:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) - (clobber (match_scratch:GPR 4 "=X,X,X,r"))] + [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") + (ior:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) + (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) + (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) + (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ orc %3,%1,%0\;orc %3,%3,%2 - orc %0,%1,%0\;orc %0,%0,%2 - orc %1,%1,%0\;orc %1,%1,%2 + orc %3,%1,%0\;orc %3,%3,%2 + orc %3,%1,%0\;orc %3,%3,%2 orc %4,%1,%0\;orc %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: scalar outer: orc op orc rtl ior inv 0 comp 1 -;; inner: xor op xor rtl xor inv 0 comp 0 +;; scalar xor -> orc (define_insn "*fuse_xor_orc" - [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r") - (ior:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) - (clobber (match_scratch:GPR 4 "=X,X,X,r"))] + [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") + (ior:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") + (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) + (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) + (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ xor %3,%1,%0\;orc %3,%3,%2 - xor %0,%1,%0\;orc %0,%0,%2 - xor %1,%1,%0\;orc %1,%1,%2 + xor %3,%1,%0\;orc %3,%3,%2 + xor %3,%1,%0\;orc %3,%3,%2 xor %4,%1,%0\;orc %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: scalar outer: xor op xor rtl xor inv 0 comp 0 -;; inner: and op and rtl and inv 0 comp 0 +;; scalar and -> xor (define_insn "*fuse_and_xor" - [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r") - (xor:GPR (and:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) - (clobber (match_scratch:GPR 4 "=X,X,X,r"))] + [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") + (xor:GPR (and:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") + (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) + (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) + (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ and %3,%1,%0\;xor %3,%3,%2 - and %0,%1,%0\;xor %0,%0,%2 - and %1,%1,%0\;xor %1,%1,%2 + and %3,%1,%0\;xor %3,%3,%2 + and %3,%1,%0\;xor %3,%3,%2 and %4,%1,%0\;xor %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: scalar outer: xor op xor rtl xor inv 0 comp 0 -;; inner: andc op andc rtl and inv 0 comp 1 +;; scalar andc -> xor (define_insn "*fuse_andc_xor" - [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r") - (xor:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) - (clobber (match_scratch:GPR 4 "=X,X,X,r"))] + [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") + (xor:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) + (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) + (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) + (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ andc %3,%1,%0\;xor %3,%3,%2 - andc %0,%1,%0\;xor %0,%0,%2 - andc %1,%1,%0\;xor %1,%1,%2 + andc %3,%1,%0\;xor %3,%3,%2 + andc %3,%1,%0\;xor %3,%3,%2 andc %4,%1,%0\;xor %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: scalar outer: xor op xor rtl xor inv 0 comp 0 -;; inner: eqv op eqv rtl xor inv 1 comp 0 +;; scalar eqv -> xor (define_insn "*fuse_eqv_xor" - [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r") - (xor:GPR (not:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) - (clobber (match_scratch:GPR 4 "=X,X,X,r"))] + [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") + (xor:GPR (not:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") + (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) + (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) + (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ eqv %3,%1,%0\;xor %3,%3,%2 - eqv %0,%1,%0\;xor %0,%0,%2 - eqv %1,%1,%0\;xor %1,%1,%2 + eqv %3,%1,%0\;xor %3,%3,%2 + eqv %3,%1,%0\;xor %3,%3,%2 eqv %4,%1,%0\;xor %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: scalar outer: xor op xor rtl xor inv 0 comp 0 -;; inner: nand op nand rtl ior inv 0 comp 3 +;; scalar nand -> xor (define_insn "*fuse_nand_xor" - [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r") - (xor:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) - (clobber (match_scratch:GPR 4 "=X,X,X,r"))] + [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") + (xor:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) + (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) + (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) + (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ nand %3,%1,%0\;xor %3,%3,%2 - nand %0,%1,%0\;xor %0,%0,%2 - nand %1,%1,%0\;xor %1,%1,%2 + nand %3,%1,%0\;xor %3,%3,%2 + nand %3,%1,%0\;xor %3,%3,%2 nand %4,%1,%0\;xor %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: scalar outer: xor op xor rtl xor inv 0 comp 0 -;; inner: nor op nor rtl and inv 0 comp 3 +;; scalar nor -> xor (define_insn "*fuse_nor_xor" - [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r") - (xor:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) - (clobber (match_scratch:GPR 4 "=X,X,X,r"))] + [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") + (xor:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) + (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) + (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) + (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ nor %3,%1,%0\;xor %3,%3,%2 - nor %0,%1,%0\;xor %0,%0,%2 - nor %1,%1,%0\;xor %1,%1,%2 + nor %3,%1,%0\;xor %3,%3,%2 + nor %3,%1,%0\;xor %3,%3,%2 nor %4,%1,%0\;xor %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: scalar outer: xor op xor rtl xor inv 0 comp 0 -;; inner: or op or rtl ior inv 0 comp 0 +;; scalar or -> xor (define_insn "*fuse_or_xor" - [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r") - (xor:GPR (ior:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) - (clobber (match_scratch:GPR 4 "=X,X,X,r"))] + [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") + (xor:GPR (ior:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") + (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) + (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) + (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ or %3,%1,%0\;xor %3,%3,%2 - or %0,%1,%0\;xor %0,%0,%2 - or %1,%1,%0\;xor %1,%1,%2 + or %3,%1,%0\;xor %3,%3,%2 + or %3,%1,%0\;xor %3,%3,%2 or %4,%1,%0\;xor %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: scalar outer: xor op xor rtl xor inv 0 comp 0 -;; inner: orc op orc rtl ior inv 0 comp 1 +;; scalar orc -> xor (define_insn "*fuse_orc_xor" - [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r") - (xor:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) - (clobber (match_scratch:GPR 4 "=X,X,X,r"))] + [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") + (xor:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) + (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) + (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) + (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ orc %3,%1,%0\;xor %3,%3,%2 - orc %0,%1,%0\;xor %0,%0,%2 - orc %1,%1,%0\;xor %1,%1,%2 + orc %3,%1,%0\;xor %3,%3,%2 + orc %3,%1,%0\;xor %3,%3,%2 orc %4,%1,%0\;xor %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: scalar outer: xor op xor rtl xor inv 0 comp 0 -;; inner: xor op xor rtl xor inv 0 comp 0 +;; scalar xor -> xor (define_insn "*fuse_xor_xor" - [(set (match_operand:GPR 3 "gpc_reg_operand" "=&r,0,1,r") - (xor:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") (match_operand:GPR 1 "gpc_reg_operand" "%r,r,r,r")) (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) - (clobber (match_scratch:GPR 4 "=X,X,X,r"))] + [(set (match_operand:GPR 3 "gpc_reg_operand" "=0,1,&r,r") + (xor:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") + (match_operand:GPR 1 "gpc_reg_operand" "%r,r,r,r")) + (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) + (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ xor %3,%1,%0\;xor %3,%3,%2 - xor %0,%1,%0\;xor %0,%0,%2 - xor %1,%1,%0\;xor %1,%1,%2 + xor %3,%1,%0\;xor %3,%3,%2 + xor %3,%1,%0\;xor %3,%3,%2 xor %4,%1,%0\;xor %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: vector outer: and op vand rtl and inv 0 comp 0 -;; inner: and op vand rtl and inv 0 comp 0 +;; vector vand -> vand (define_insn "*fuse_vand_vand" - [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v") - (and:VM (and:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") (match_operand:VM 1 "altivec_register_operand" "%v,v,v,v")) (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) - (clobber (match_scratch:VM 4 "=X,X,X,r"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") + (and:VM (and:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") + (match_operand:VM 1 "altivec_register_operand" "%v,v,v,v")) + (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) + (clobber (match_scratch:VM 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ vand %3,%1,%0\;vand %3,%3,%2 - vand %0,%1,%0\;vand %0,%0,%2 - vand %1,%1,%0\;vand %1,%1,%2 + vand %3,%1,%0\;vand %3,%3,%2 + vand %3,%1,%0\;vand %3,%3,%2 vand %4,%1,%0\;vand %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: vector outer: and op vand rtl and inv 0 comp 0 -;; inner: andc op vandc rtl and inv 0 comp 1 +;; vector vandc -> vand (define_insn "*fuse_vandc_vand" - [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v") - (and:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) - (clobber (match_scratch:VM 4 "=X,X,X,r"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") + (and:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) + (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) + (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) + (clobber (match_scratch:VM 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ vandc %3,%1,%0\;vand %3,%3,%2 - vandc %0,%1,%0\;vand %0,%0,%2 - vandc %1,%1,%0\;vand %1,%1,%2 + vandc %3,%1,%0\;vand %3,%3,%2 + vandc %3,%1,%0\;vand %3,%3,%2 vandc %4,%1,%0\;vand %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: vector outer: and op vand rtl and inv 0 comp 0 -;; inner: eqv op veqv rtl xor inv 1 comp 0 +;; vector veqv -> vand (define_insn "*fuse_veqv_vand" - [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v") - (and:VM (not:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) - (clobber (match_scratch:VM 4 "=X,X,X,r"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") + (and:VM (not:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") + (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) + (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) + (clobber (match_scratch:VM 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ veqv %3,%1,%0\;vand %3,%3,%2 - veqv %0,%1,%0\;vand %0,%0,%2 - veqv %1,%1,%0\;vand %1,%1,%2 + veqv %3,%1,%0\;vand %3,%3,%2 + veqv %3,%1,%0\;vand %3,%3,%2 veqv %4,%1,%0\;vand %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: vector outer: and op vand rtl and inv 0 comp 0 -;; inner: nand op vnand rtl ior inv 0 comp 3 +;; vector vnand -> vand (define_insn "*fuse_vnand_vand" - [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v") - (and:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) (not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) - (clobber (match_scratch:VM 4 "=X,X,X,r"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") + (and:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) + (not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) + (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) + (clobber (match_scratch:VM 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ vnand %3,%1,%0\;vand %3,%3,%2 - vnand %0,%1,%0\;vand %0,%0,%2 - vnand %1,%1,%0\;vand %1,%1,%2 + vnand %3,%1,%0\;vand %3,%3,%2 + vnand %3,%1,%0\;vand %3,%3,%2 vnand %4,%1,%0\;vand %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: vector outer: and op vand rtl and inv 0 comp 0 -;; inner: nor op vnor rtl and inv 0 comp 3 +;; vector vnor -> vand (define_insn "*fuse_vnor_vand" - [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v") - (and:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) (not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) - (clobber (match_scratch:VM 4 "=X,X,X,r"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") + (and:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) + (not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) + (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) + (clobber (match_scratch:VM 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ vnor %3,%1,%0\;vand %3,%3,%2 - vnor %0,%1,%0\;vand %0,%0,%2 - vnor %1,%1,%0\;vand %1,%1,%2 + vnor %3,%1,%0\;vand %3,%3,%2 + vnor %3,%1,%0\;vand %3,%3,%2 vnor %4,%1,%0\;vand %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: vector outer: and op vand rtl and inv 0 comp 0 -;; inner: or op vor rtl ior inv 0 comp 0 +;; vector vor -> vand (define_insn "*fuse_vor_vand" - [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v") - (and:VM (ior:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) - (clobber (match_scratch:VM 4 "=X,X,X,r"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") + (and:VM (ior:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") + (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) + (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) + (clobber (match_scratch:VM 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ vor %3,%1,%0\;vand %3,%3,%2 - vor %0,%1,%0\;vand %0,%0,%2 - vor %1,%1,%0\;vand %1,%1,%2 + vor %3,%1,%0\;vand %3,%3,%2 + vor %3,%1,%0\;vand %3,%3,%2 vor %4,%1,%0\;vand %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: vector outer: and op vand rtl and inv 0 comp 0 -;; inner: orc op vorc rtl ior inv 0 comp 1 +;; vector vorc -> vand (define_insn "*fuse_vorc_vand" - [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v") - (and:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) - (clobber (match_scratch:VM 4 "=X,X,X,r"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") + (and:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) + (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) + (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) + (clobber (match_scratch:VM 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ vorc %3,%1,%0\;vand %3,%3,%2 - vorc %0,%1,%0\;vand %0,%0,%2 - vorc %1,%1,%0\;vand %1,%1,%2 + vorc %3,%1,%0\;vand %3,%3,%2 + vorc %3,%1,%0\;vand %3,%3,%2 vorc %4,%1,%0\;vand %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: vector outer: and op vand rtl and inv 0 comp 0 -;; inner: xor op vxor rtl xor inv 0 comp 0 +;; vector vxor -> vand (define_insn "*fuse_vxor_vand" - [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v") - (and:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) - (clobber (match_scratch:VM 4 "=X,X,X,r"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") + (and:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") + (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) + (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) + (clobber (match_scratch:VM 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ vxor %3,%1,%0\;vand %3,%3,%2 - vxor %0,%1,%0\;vand %0,%0,%2 - vxor %1,%1,%0\;vand %1,%1,%2 + vxor %3,%1,%0\;vand %3,%3,%2 + vxor %3,%1,%0\;vand %3,%3,%2 vxor %4,%1,%0\;vand %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: vector outer: andc op vandc rtl and inv 0 comp 1 -;; inner: and op vand rtl and inv 0 comp 0 +;; vector vand -> vandc (define_insn "*fuse_vand_vandc" - [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v") - (and:VM (and:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) - (clobber (match_scratch:VM 4 "=X,X,X,r"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") + (and:VM (and:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") + (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) + (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) + (clobber (match_scratch:VM 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ vand %3,%1,%0\;vandc %3,%3,%2 - vand %0,%1,%0\;vandc %0,%0,%2 - vand %1,%1,%0\;vandc %1,%1,%2 + vand %3,%1,%0\;vandc %3,%3,%2 + vand %3,%1,%0\;vandc %3,%3,%2 vand %4,%1,%0\;vandc %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: vector outer: andc op vandc rtl and inv 0 comp 1 -;; inner: andc op vandc rtl and inv 0 comp 1 +;; vector vandc -> vandc (define_insn "*fuse_vandc_vandc" - [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v") - (and:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) - (clobber (match_scratch:VM 4 "=X,X,X,r"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") + (and:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) + (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) + (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) + (clobber (match_scratch:VM 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ vandc %3,%1,%0\;vandc %3,%3,%2 - vandc %0,%1,%0\;vandc %0,%0,%2 - vandc %1,%1,%0\;vandc %1,%1,%2 + vandc %3,%1,%0\;vandc %3,%3,%2 + vandc %3,%1,%0\;vandc %3,%3,%2 vandc %4,%1,%0\;vandc %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: vector outer: andc op vandc rtl and inv 0 comp 1 -;; inner: eqv op veqv rtl xor inv 1 comp 0 +;; vector veqv -> vandc (define_insn "*fuse_veqv_vandc" - [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v") - (and:VM (not:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) - (clobber (match_scratch:VM 4 "=X,X,X,r"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") + (and:VM (not:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") + (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) + (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) + (clobber (match_scratch:VM 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ veqv %3,%1,%0\;vandc %3,%3,%2 - veqv %0,%1,%0\;vandc %0,%0,%2 - veqv %1,%1,%0\;vandc %1,%1,%2 + veqv %3,%1,%0\;vandc %3,%3,%2 + veqv %3,%1,%0\;vandc %3,%3,%2 veqv %4,%1,%0\;vandc %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: vector outer: andc op vandc rtl and inv 0 comp 1 -;; inner: nand op vnand rtl ior inv 0 comp 3 +;; vector vnand -> vandc (define_insn "*fuse_vnand_vandc" - [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v") - (and:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) (not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) - (clobber (match_scratch:VM 4 "=X,X,X,r"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") + (and:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) + (not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) + (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) + (clobber (match_scratch:VM 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ vnand %3,%1,%0\;vandc %3,%3,%2 - vnand %0,%1,%0\;vandc %0,%0,%2 - vnand %1,%1,%0\;vandc %1,%1,%2 + vnand %3,%1,%0\;vandc %3,%3,%2 + vnand %3,%1,%0\;vandc %3,%3,%2 vnand %4,%1,%0\;vandc %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: vector outer: andc op vandc rtl and inv 0 comp 1 -;; inner: nor op vnor rtl and inv 0 comp 3 +;; vector vnor -> vandc (define_insn "*fuse_vnor_vandc" - [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v") - (and:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) (not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) - (clobber (match_scratch:VM 4 "=X,X,X,r"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") + (and:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) + (not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) + (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) + (clobber (match_scratch:VM 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ vnor %3,%1,%0\;vandc %3,%3,%2 - vnor %0,%1,%0\;vandc %0,%0,%2 - vnor %1,%1,%0\;vandc %1,%1,%2 + vnor %3,%1,%0\;vandc %3,%3,%2 + vnor %3,%1,%0\;vandc %3,%3,%2 vnor %4,%1,%0\;vandc %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: vector outer: andc op vandc rtl and inv 0 comp 1 -;; inner: or op vor rtl ior inv 0 comp 0 +;; vector vor -> vandc (define_insn "*fuse_vor_vandc" - [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v") - (and:VM (ior:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) - (clobber (match_scratch:VM 4 "=X,X,X,r"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") + (and:VM (ior:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") + (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) + (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) + (clobber (match_scratch:VM 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ vor %3,%1,%0\;vandc %3,%3,%2 - vor %0,%1,%0\;vandc %0,%0,%2 - vor %1,%1,%0\;vandc %1,%1,%2 + vor %3,%1,%0\;vandc %3,%3,%2 + vor %3,%1,%0\;vandc %3,%3,%2 vor %4,%1,%0\;vandc %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: vector outer: andc op vandc rtl and inv 0 comp 1 -;; inner: orc op vorc rtl ior inv 0 comp 1 +;; vector vorc -> vandc (define_insn "*fuse_vorc_vandc" - [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v") - (and:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) - (clobber (match_scratch:VM 4 "=X,X,X,r"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") + (and:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) + (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) + (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) + (clobber (match_scratch:VM 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ vorc %3,%1,%0\;vandc %3,%3,%2 - vorc %0,%1,%0\;vandc %0,%0,%2 - vorc %1,%1,%0\;vandc %1,%1,%2 + vorc %3,%1,%0\;vandc %3,%3,%2 + vorc %3,%1,%0\;vandc %3,%3,%2 vorc %4,%1,%0\;vandc %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: vector outer: andc op vandc rtl and inv 0 comp 1 -;; inner: xor op vxor rtl xor inv 0 comp 0 +;; vector vxor -> vandc (define_insn "*fuse_vxor_vandc" - [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v") - (and:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) - (clobber (match_scratch:VM 4 "=X,X,X,r"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") + (and:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") + (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) + (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) + (clobber (match_scratch:VM 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ vxor %3,%1,%0\;vandc %3,%3,%2 - vxor %0,%1,%0\;vandc %0,%0,%2 - vxor %1,%1,%0\;vandc %1,%1,%2 + vxor %3,%1,%0\;vandc %3,%3,%2 + vxor %3,%1,%0\;vandc %3,%3,%2 vxor %4,%1,%0\;vandc %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: vector outer: eqv op veqv rtl xor inv 1 comp 0 -;; inner: and op vand rtl and inv 0 comp 0 +;; vector vand -> veqv (define_insn "*fuse_vand_veqv" - [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v") - (not:VM (xor:VM (and:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) - (clobber (match_scratch:VM 4 "=X,X,X,r"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") + (not:VM (xor:VM (and:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") + (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) + (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) + (clobber (match_scratch:VM 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ vand %3,%1,%0\;veqv %3,%3,%2 - vand %0,%1,%0\;veqv %0,%0,%2 - vand %1,%1,%0\;veqv %1,%1,%2 + vand %3,%1,%0\;veqv %3,%3,%2 + vand %3,%1,%0\;veqv %3,%3,%2 vand %4,%1,%0\;veqv %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: vector outer: eqv op veqv rtl xor inv 1 comp 0 -;; inner: andc op vandc rtl and inv 0 comp 1 +;; vector vandc -> veqv (define_insn "*fuse_vandc_veqv" - [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v") - (not:VM (xor:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) - (clobber (match_scratch:VM 4 "=X,X,X,r"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") + (not:VM (xor:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) + (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) + (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) + (clobber (match_scratch:VM 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ vandc %3,%1,%0\;veqv %3,%3,%2 - vandc %0,%1,%0\;veqv %0,%0,%2 - vandc %1,%1,%0\;veqv %1,%1,%2 + vandc %3,%1,%0\;veqv %3,%3,%2 + vandc %3,%1,%0\;veqv %3,%3,%2 vandc %4,%1,%0\;veqv %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: vector outer: eqv op veqv rtl xor inv 1 comp 0 -;; inner: eqv op veqv rtl xor inv 1 comp 0 +;; vector veqv -> veqv (define_insn "*fuse_veqv_veqv" - [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v") - (not:VM (xor:VM (not:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") (match_operand:VM 1 "altivec_register_operand" "%v,v,v,v"))) (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) - (clobber (match_scratch:VM 4 "=X,X,X,r"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") + (not:VM (xor:VM (not:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") + (match_operand:VM 1 "altivec_register_operand" "%v,v,v,v"))) + (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) + (clobber (match_scratch:VM 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ veqv %3,%1,%0\;veqv %3,%3,%2 - veqv %0,%1,%0\;veqv %0,%0,%2 - veqv %1,%1,%0\;veqv %1,%1,%2 + veqv %3,%1,%0\;veqv %3,%3,%2 + veqv %3,%1,%0\;veqv %3,%3,%2 veqv %4,%1,%0\;veqv %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: vector outer: eqv op veqv rtl xor inv 1 comp 0 -;; inner: nand op vnand rtl ior inv 0 comp 3 +;; vector vnand -> veqv (define_insn "*fuse_vnand_veqv" - [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v") - (not:VM (xor:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) (not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) - (clobber (match_scratch:VM 4 "=X,X,X,r"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") + (not:VM (xor:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) + (not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) + (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) + (clobber (match_scratch:VM 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ vnand %3,%1,%0\;veqv %3,%3,%2 - vnand %0,%1,%0\;veqv %0,%0,%2 - vnand %1,%1,%0\;veqv %1,%1,%2 + vnand %3,%1,%0\;veqv %3,%3,%2 + vnand %3,%1,%0\;veqv %3,%3,%2 vnand %4,%1,%0\;veqv %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: vector outer: eqv op veqv rtl xor inv 1 comp 0 -;; inner: nor op vnor rtl and inv 0 comp 3 +;; vector vnor -> veqv (define_insn "*fuse_vnor_veqv" - [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v") - (not:VM (xor:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) (not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) - (clobber (match_scratch:VM 4 "=X,X,X,r"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") + (not:VM (xor:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) + (not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) + (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) + (clobber (match_scratch:VM 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ vnor %3,%1,%0\;veqv %3,%3,%2 - vnor %0,%1,%0\;veqv %0,%0,%2 - vnor %1,%1,%0\;veqv %1,%1,%2 + vnor %3,%1,%0\;veqv %3,%3,%2 + vnor %3,%1,%0\;veqv %3,%3,%2 vnor %4,%1,%0\;veqv %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: vector outer: eqv op veqv rtl xor inv 1 comp 0 -;; inner: or op vor rtl ior inv 0 comp 0 +;; vector vor -> veqv (define_insn "*fuse_vor_veqv" - [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v") - (not:VM (xor:VM (ior:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) - (clobber (match_scratch:VM 4 "=X,X,X,r"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") + (not:VM (xor:VM (ior:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") + (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) + (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) + (clobber (match_scratch:VM 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ vor %3,%1,%0\;veqv %3,%3,%2 - vor %0,%1,%0\;veqv %0,%0,%2 - vor %1,%1,%0\;veqv %1,%1,%2 + vor %3,%1,%0\;veqv %3,%3,%2 + vor %3,%1,%0\;veqv %3,%3,%2 vor %4,%1,%0\;veqv %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: vector outer: eqv op veqv rtl xor inv 1 comp 0 -;; inner: orc op vorc rtl ior inv 0 comp 1 +;; vector vorc -> veqv (define_insn "*fuse_vorc_veqv" - [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v") - (not:VM (xor:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) - (clobber (match_scratch:VM 4 "=X,X,X,r"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") + (not:VM (xor:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) + (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) + (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) + (clobber (match_scratch:VM 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ vorc %3,%1,%0\;veqv %3,%3,%2 - vorc %0,%1,%0\;veqv %0,%0,%2 - vorc %1,%1,%0\;veqv %1,%1,%2 + vorc %3,%1,%0\;veqv %3,%3,%2 + vorc %3,%1,%0\;veqv %3,%3,%2 vorc %4,%1,%0\;veqv %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: vector outer: eqv op veqv rtl xor inv 1 comp 0 -;; inner: xor op vxor rtl xor inv 0 comp 0 +;; vector vxor -> veqv (define_insn "*fuse_vxor_veqv" - [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v") - (not:VM (xor:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) - (clobber (match_scratch:VM 4 "=X,X,X,r"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") + (not:VM (xor:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") + (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) + (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) + (clobber (match_scratch:VM 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ vxor %3,%1,%0\;veqv %3,%3,%2 - vxor %0,%1,%0\;veqv %0,%0,%2 - vxor %1,%1,%0\;veqv %1,%1,%2 + vxor %3,%1,%0\;veqv %3,%3,%2 + vxor %3,%1,%0\;veqv %3,%3,%2 vxor %4,%1,%0\;veqv %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: vector outer: nand op vnand rtl ior inv 0 comp 3 -;; inner: and op vand rtl and inv 0 comp 0 +;; vector vand -> vnand (define_insn "*fuse_vand_vnand" - [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v") - (ior:VM (not:VM (and:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) - (clobber (match_scratch:VM 4 "=X,X,X,r"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") + (ior:VM (not:VM (and:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") + (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) + (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) + (clobber (match_scratch:VM 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ vand %3,%1,%0\;vnand %3,%3,%2 - vand %0,%1,%0\;vnand %0,%0,%2 - vand %1,%1,%0\;vnand %1,%1,%2 + vand %3,%1,%0\;vnand %3,%3,%2 + vand %3,%1,%0\;vnand %3,%3,%2 vand %4,%1,%0\;vnand %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: vector outer: nand op vnand rtl ior inv 0 comp 3 -;; inner: andc op vandc rtl and inv 0 comp 1 +;; vector vandc -> vnand (define_insn "*fuse_vandc_vnand" - [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v") - (ior:VM (not:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) - (clobber (match_scratch:VM 4 "=X,X,X,r"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") + (ior:VM (not:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) + (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) + (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) + (clobber (match_scratch:VM 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ vandc %3,%1,%0\;vnand %3,%3,%2 - vandc %0,%1,%0\;vnand %0,%0,%2 - vandc %1,%1,%0\;vnand %1,%1,%2 + vandc %3,%1,%0\;vnand %3,%3,%2 + vandc %3,%1,%0\;vnand %3,%3,%2 vandc %4,%1,%0\;vnand %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: vector outer: nand op vnand rtl ior inv 0 comp 3 -;; inner: eqv op veqv rtl xor inv 1 comp 0 +;; vector veqv -> vnand (define_insn "*fuse_veqv_vnand" - [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v") - (ior:VM (not:VM (not:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")))) (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) - (clobber (match_scratch:VM 4 "=X,X,X,r"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") + (ior:VM (not:VM (not:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") + (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")))) + (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) + (clobber (match_scratch:VM 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ veqv %3,%1,%0\;vnand %3,%3,%2 - veqv %0,%1,%0\;vnand %0,%0,%2 - veqv %1,%1,%0\;vnand %1,%1,%2 + veqv %3,%1,%0\;vnand %3,%3,%2 + veqv %3,%1,%0\;vnand %3,%3,%2 veqv %4,%1,%0\;vnand %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: vector outer: nand op vnand rtl ior inv 0 comp 3 -;; inner: nand op vnand rtl ior inv 0 comp 3 +;; vector vnand -> vnand (define_insn "*fuse_vnand_vnand" - [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v") - (ior:VM (not:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) (not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")))) (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) - (clobber (match_scratch:VM 4 "=X,X,X,r"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") + (ior:VM (not:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) + (not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")))) + (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) + (clobber (match_scratch:VM 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ vnand %3,%1,%0\;vnand %3,%3,%2 - vnand %0,%1,%0\;vnand %0,%0,%2 - vnand %1,%1,%0\;vnand %1,%1,%2 + vnand %3,%1,%0\;vnand %3,%3,%2 + vnand %3,%1,%0\;vnand %3,%3,%2 vnand %4,%1,%0\;vnand %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: vector outer: nand op vnand rtl ior inv 0 comp 3 -;; inner: nor op vnor rtl and inv 0 comp 3 +;; vector vnor -> vnand (define_insn "*fuse_vnor_vnand" - [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v") - (ior:VM (not:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) (not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")))) (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) - (clobber (match_scratch:VM 4 "=X,X,X,r"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") + (ior:VM (not:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) + (not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")))) + (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) + (clobber (match_scratch:VM 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ vnor %3,%1,%0\;vnand %3,%3,%2 - vnor %0,%1,%0\;vnand %0,%0,%2 - vnor %1,%1,%0\;vnand %1,%1,%2 + vnor %3,%1,%0\;vnand %3,%3,%2 + vnor %3,%1,%0\;vnand %3,%3,%2 vnor %4,%1,%0\;vnand %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: vector outer: nand op vnand rtl ior inv 0 comp 3 -;; inner: or op vor rtl ior inv 0 comp 0 +;; vector vor -> vnand (define_insn "*fuse_vor_vnand" - [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v") - (ior:VM (not:VM (ior:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) - (clobber (match_scratch:VM 4 "=X,X,X,r"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") + (ior:VM (not:VM (ior:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") + (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) + (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) + (clobber (match_scratch:VM 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ vor %3,%1,%0\;vnand %3,%3,%2 - vor %0,%1,%0\;vnand %0,%0,%2 - vor %1,%1,%0\;vnand %1,%1,%2 + vor %3,%1,%0\;vnand %3,%3,%2 + vor %3,%1,%0\;vnand %3,%3,%2 vor %4,%1,%0\;vnand %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: vector outer: nand op vnand rtl ior inv 0 comp 3 -;; inner: orc op vorc rtl ior inv 0 comp 1 +;; vector vorc -> vnand (define_insn "*fuse_vorc_vnand" - [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v") - (ior:VM (not:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) - (clobber (match_scratch:VM 4 "=X,X,X,r"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") + (ior:VM (not:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) + (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) + (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) + (clobber (match_scratch:VM 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ vorc %3,%1,%0\;vnand %3,%3,%2 - vorc %0,%1,%0\;vnand %0,%0,%2 - vorc %1,%1,%0\;vnand %1,%1,%2 + vorc %3,%1,%0\;vnand %3,%3,%2 + vorc %3,%1,%0\;vnand %3,%3,%2 vorc %4,%1,%0\;vnand %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: vector outer: nand op vnand rtl ior inv 0 comp 3 -;; inner: xor op vxor rtl xor inv 0 comp 0 +;; vector vxor -> vnand (define_insn "*fuse_vxor_vnand" - [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v") - (ior:VM (not:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) - (clobber (match_scratch:VM 4 "=X,X,X,r"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") + (ior:VM (not:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") + (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) + (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) + (clobber (match_scratch:VM 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ vxor %3,%1,%0\;vnand %3,%3,%2 - vxor %0,%1,%0\;vnand %0,%0,%2 - vxor %1,%1,%0\;vnand %1,%1,%2 + vxor %3,%1,%0\;vnand %3,%3,%2 + vxor %3,%1,%0\;vnand %3,%3,%2 vxor %4,%1,%0\;vnand %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: vector outer: nor op vnor rtl and inv 0 comp 3 -;; inner: and op vand rtl and inv 0 comp 0 +;; vector vand -> vnor (define_insn "*fuse_vand_vnor" - [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v") - (and:VM (not:VM (and:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) - (clobber (match_scratch:VM 4 "=X,X,X,r"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") + (and:VM (not:VM (and:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") + (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) + (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) + (clobber (match_scratch:VM 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ vand %3,%1,%0\;vnor %3,%3,%2 - vand %0,%1,%0\;vnor %0,%0,%2 - vand %1,%1,%0\;vnor %1,%1,%2 + vand %3,%1,%0\;vnor %3,%3,%2 + vand %3,%1,%0\;vnor %3,%3,%2 vand %4,%1,%0\;vnor %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: vector outer: nor op vnor rtl and inv 0 comp 3 -;; inner: andc op vandc rtl and inv 0 comp 1 +;; vector vandc -> vnor (define_insn "*fuse_vandc_vnor" - [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v") - (and:VM (not:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) - (clobber (match_scratch:VM 4 "=X,X,X,r"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") + (and:VM (not:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) + (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) + (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) + (clobber (match_scratch:VM 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ vandc %3,%1,%0\;vnor %3,%3,%2 - vandc %0,%1,%0\;vnor %0,%0,%2 - vandc %1,%1,%0\;vnor %1,%1,%2 + vandc %3,%1,%0\;vnor %3,%3,%2 + vandc %3,%1,%0\;vnor %3,%3,%2 vandc %4,%1,%0\;vnor %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: vector outer: nor op vnor rtl and inv 0 comp 3 -;; inner: eqv op veqv rtl xor inv 1 comp 0 +;; vector veqv -> vnor (define_insn "*fuse_veqv_vnor" - [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v") - (and:VM (not:VM (not:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")))) (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) - (clobber (match_scratch:VM 4 "=X,X,X,r"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") + (and:VM (not:VM (not:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") + (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")))) + (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) + (clobber (match_scratch:VM 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ veqv %3,%1,%0\;vnor %3,%3,%2 - veqv %0,%1,%0\;vnor %0,%0,%2 - veqv %1,%1,%0\;vnor %1,%1,%2 + veqv %3,%1,%0\;vnor %3,%3,%2 + veqv %3,%1,%0\;vnor %3,%3,%2 veqv %4,%1,%0\;vnor %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: vector outer: nor op vnor rtl and inv 0 comp 3 -;; inner: nand op vnand rtl ior inv 0 comp 3 +;; vector vnand -> vnor (define_insn "*fuse_vnand_vnor" - [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v") - (and:VM (not:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) (not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")))) (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) - (clobber (match_scratch:VM 4 "=X,X,X,r"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") + (and:VM (not:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) + (not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")))) + (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) + (clobber (match_scratch:VM 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ vnand %3,%1,%0\;vnor %3,%3,%2 - vnand %0,%1,%0\;vnor %0,%0,%2 - vnand %1,%1,%0\;vnor %1,%1,%2 + vnand %3,%1,%0\;vnor %3,%3,%2 + vnand %3,%1,%0\;vnor %3,%3,%2 vnand %4,%1,%0\;vnor %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: vector outer: nor op vnor rtl and inv 0 comp 3 -;; inner: nor op vnor rtl and inv 0 comp 3 +;; vector vnor -> vnor (define_insn "*fuse_vnor_vnor" - [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v") - (and:VM (not:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) (not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")))) (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) - (clobber (match_scratch:VM 4 "=X,X,X,r"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") + (and:VM (not:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) + (not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")))) + (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) + (clobber (match_scratch:VM 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ vnor %3,%1,%0\;vnor %3,%3,%2 - vnor %0,%1,%0\;vnor %0,%0,%2 - vnor %1,%1,%0\;vnor %1,%1,%2 + vnor %3,%1,%0\;vnor %3,%3,%2 + vnor %3,%1,%0\;vnor %3,%3,%2 vnor %4,%1,%0\;vnor %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: vector outer: nor op vnor rtl and inv 0 comp 3 -;; inner: or op vor rtl ior inv 0 comp 0 +;; vector vor -> vnor (define_insn "*fuse_vor_vnor" - [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v") - (and:VM (not:VM (ior:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) - (clobber (match_scratch:VM 4 "=X,X,X,r"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") + (and:VM (not:VM (ior:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") + (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) + (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) + (clobber (match_scratch:VM 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ vor %3,%1,%0\;vnor %3,%3,%2 - vor %0,%1,%0\;vnor %0,%0,%2 - vor %1,%1,%0\;vnor %1,%1,%2 + vor %3,%1,%0\;vnor %3,%3,%2 + vor %3,%1,%0\;vnor %3,%3,%2 vor %4,%1,%0\;vnor %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: vector outer: nor op vnor rtl and inv 0 comp 3 -;; inner: orc op vorc rtl ior inv 0 comp 1 +;; vector vorc -> vnor (define_insn "*fuse_vorc_vnor" - [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v") - (and:VM (not:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) - (clobber (match_scratch:VM 4 "=X,X,X,r"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") + (and:VM (not:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) + (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) + (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) + (clobber (match_scratch:VM 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ vorc %3,%1,%0\;vnor %3,%3,%2 - vorc %0,%1,%0\;vnor %0,%0,%2 - vorc %1,%1,%0\;vnor %1,%1,%2 + vorc %3,%1,%0\;vnor %3,%3,%2 + vorc %3,%1,%0\;vnor %3,%3,%2 vorc %4,%1,%0\;vnor %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: vector outer: nor op vnor rtl and inv 0 comp 3 -;; inner: xor op vxor rtl xor inv 0 comp 0 +;; vector vxor -> vnor (define_insn "*fuse_vxor_vnor" - [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v") - (and:VM (not:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) - (clobber (match_scratch:VM 4 "=X,X,X,r"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") + (and:VM (not:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") + (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) + (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) + (clobber (match_scratch:VM 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ vxor %3,%1,%0\;vnor %3,%3,%2 - vxor %0,%1,%0\;vnor %0,%0,%2 - vxor %1,%1,%0\;vnor %1,%1,%2 + vxor %3,%1,%0\;vnor %3,%3,%2 + vxor %3,%1,%0\;vnor %3,%3,%2 vxor %4,%1,%0\;vnor %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: vector outer: or op vor rtl ior inv 0 comp 0 -;; inner: and op vand rtl and inv 0 comp 0 +;; vector vand -> vor (define_insn "*fuse_vand_vor" - [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v") - (ior:VM (and:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) - (clobber (match_scratch:VM 4 "=X,X,X,r"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") + (ior:VM (and:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") + (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) + (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) + (clobber (match_scratch:VM 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ vand %3,%1,%0\;vor %3,%3,%2 - vand %0,%1,%0\;vor %0,%0,%2 - vand %1,%1,%0\;vor %1,%1,%2 + vand %3,%1,%0\;vor %3,%3,%2 + vand %3,%1,%0\;vor %3,%3,%2 vand %4,%1,%0\;vor %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: vector outer: or op vor rtl ior inv 0 comp 0 -;; inner: andc op vandc rtl and inv 0 comp 1 +;; vector vandc -> vor (define_insn "*fuse_vandc_vor" - [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v") - (ior:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) - (clobber (match_scratch:VM 4 "=X,X,X,r"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") + (ior:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) + (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) + (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) + (clobber (match_scratch:VM 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ vandc %3,%1,%0\;vor %3,%3,%2 - vandc %0,%1,%0\;vor %0,%0,%2 - vandc %1,%1,%0\;vor %1,%1,%2 + vandc %3,%1,%0\;vor %3,%3,%2 + vandc %3,%1,%0\;vor %3,%3,%2 vandc %4,%1,%0\;vor %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: vector outer: or op vor rtl ior inv 0 comp 0 -;; inner: eqv op veqv rtl xor inv 1 comp 0 +;; vector veqv -> vor (define_insn "*fuse_veqv_vor" - [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v") - (ior:VM (not:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) - (clobber (match_scratch:VM 4 "=X,X,X,r"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") + (ior:VM (not:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") + (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) + (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) + (clobber (match_scratch:VM 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ veqv %3,%1,%0\;vor %3,%3,%2 - veqv %0,%1,%0\;vor %0,%0,%2 - veqv %1,%1,%0\;vor %1,%1,%2 + veqv %3,%1,%0\;vor %3,%3,%2 + veqv %3,%1,%0\;vor %3,%3,%2 veqv %4,%1,%0\;vor %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: vector outer: or op vor rtl ior inv 0 comp 0 -;; inner: nand op vnand rtl ior inv 0 comp 3 +;; vector vnand -> vor (define_insn "*fuse_vnand_vor" - [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v") - (ior:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) (not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) - (clobber (match_scratch:VM 4 "=X,X,X,r"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") + (ior:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) + (not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) + (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) + (clobber (match_scratch:VM 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ vnand %3,%1,%0\;vor %3,%3,%2 - vnand %0,%1,%0\;vor %0,%0,%2 - vnand %1,%1,%0\;vor %1,%1,%2 + vnand %3,%1,%0\;vor %3,%3,%2 + vnand %3,%1,%0\;vor %3,%3,%2 vnand %4,%1,%0\;vor %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: vector outer: or op vor rtl ior inv 0 comp 0 -;; inner: nor op vnor rtl and inv 0 comp 3 +;; vector vnor -> vor (define_insn "*fuse_vnor_vor" - [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v") - (ior:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) (not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) - (clobber (match_scratch:VM 4 "=X,X,X,r"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") + (ior:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) + (not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) + (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) + (clobber (match_scratch:VM 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ vnor %3,%1,%0\;vor %3,%3,%2 - vnor %0,%1,%0\;vor %0,%0,%2 - vnor %1,%1,%0\;vor %1,%1,%2 + vnor %3,%1,%0\;vor %3,%3,%2 + vnor %3,%1,%0\;vor %3,%3,%2 vnor %4,%1,%0\;vor %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: vector outer: or op vor rtl ior inv 0 comp 0 -;; inner: or op vor rtl ior inv 0 comp 0 +;; vector vor -> vor (define_insn "*fuse_vor_vor" - [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v") - (ior:VM (ior:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") (match_operand:VM 1 "altivec_register_operand" "%v,v,v,v")) (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) - (clobber (match_scratch:VM 4 "=X,X,X,r"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") + (ior:VM (ior:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") + (match_operand:VM 1 "altivec_register_operand" "%v,v,v,v")) + (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) + (clobber (match_scratch:VM 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ vor %3,%1,%0\;vor %3,%3,%2 - vor %0,%1,%0\;vor %0,%0,%2 - vor %1,%1,%0\;vor %1,%1,%2 + vor %3,%1,%0\;vor %3,%3,%2 + vor %3,%1,%0\;vor %3,%3,%2 vor %4,%1,%0\;vor %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: vector outer: or op vor rtl ior inv 0 comp 0 -;; inner: orc op vorc rtl ior inv 0 comp 1 +;; vector vorc -> vor (define_insn "*fuse_vorc_vor" - [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v") - (ior:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) - (clobber (match_scratch:VM 4 "=X,X,X,r"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") + (ior:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) + (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) + (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) + (clobber (match_scratch:VM 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ vorc %3,%1,%0\;vor %3,%3,%2 - vorc %0,%1,%0\;vor %0,%0,%2 - vorc %1,%1,%0\;vor %1,%1,%2 + vorc %3,%1,%0\;vor %3,%3,%2 + vorc %3,%1,%0\;vor %3,%3,%2 vorc %4,%1,%0\;vor %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: vector outer: or op vor rtl ior inv 0 comp 0 -;; inner: xor op vxor rtl xor inv 0 comp 0 +;; vector vxor -> vor (define_insn "*fuse_vxor_vor" - [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v") - (ior:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) - (clobber (match_scratch:VM 4 "=X,X,X,r"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") + (ior:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") + (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) + (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) + (clobber (match_scratch:VM 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ vxor %3,%1,%0\;vor %3,%3,%2 - vxor %0,%1,%0\;vor %0,%0,%2 - vxor %1,%1,%0\;vor %1,%1,%2 + vxor %3,%1,%0\;vor %3,%3,%2 + vxor %3,%1,%0\;vor %3,%3,%2 vxor %4,%1,%0\;vor %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: vector outer: orc op vorc rtl ior inv 0 comp 1 -;; inner: and op vand rtl and inv 0 comp 0 +;; vector vand -> vorc (define_insn "*fuse_vand_vorc" - [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v") - (ior:VM (and:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) - (clobber (match_scratch:VM 4 "=X,X,X,r"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") + (ior:VM (and:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") + (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) + (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) + (clobber (match_scratch:VM 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ vand %3,%1,%0\;vorc %3,%3,%2 - vand %0,%1,%0\;vorc %0,%0,%2 - vand %1,%1,%0\;vorc %1,%1,%2 + vand %3,%1,%0\;vorc %3,%3,%2 + vand %3,%1,%0\;vorc %3,%3,%2 vand %4,%1,%0\;vorc %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: vector outer: orc op vorc rtl ior inv 0 comp 1 -;; inner: andc op vandc rtl and inv 0 comp 1 +;; vector vandc -> vorc (define_insn "*fuse_vandc_vorc" - [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v") - (ior:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) - (clobber (match_scratch:VM 4 "=X,X,X,r"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") + (ior:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) + (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) + (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) + (clobber (match_scratch:VM 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ vandc %3,%1,%0\;vorc %3,%3,%2 - vandc %0,%1,%0\;vorc %0,%0,%2 - vandc %1,%1,%0\;vorc %1,%1,%2 + vandc %3,%1,%0\;vorc %3,%3,%2 + vandc %3,%1,%0\;vorc %3,%3,%2 vandc %4,%1,%0\;vorc %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: vector outer: orc op vorc rtl ior inv 0 comp 1 -;; inner: eqv op veqv rtl xor inv 1 comp 0 +;; vector veqv -> vorc (define_insn "*fuse_veqv_vorc" - [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v") - (ior:VM (not:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) - (clobber (match_scratch:VM 4 "=X,X,X,r"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") + (ior:VM (not:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") + (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) + (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) + (clobber (match_scratch:VM 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ veqv %3,%1,%0\;vorc %3,%3,%2 - veqv %0,%1,%0\;vorc %0,%0,%2 - veqv %1,%1,%0\;vorc %1,%1,%2 + veqv %3,%1,%0\;vorc %3,%3,%2 + veqv %3,%1,%0\;vorc %3,%3,%2 veqv %4,%1,%0\;vorc %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: vector outer: orc op vorc rtl ior inv 0 comp 1 -;; inner: nand op vnand rtl ior inv 0 comp 3 +;; vector vnand -> vorc (define_insn "*fuse_vnand_vorc" - [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v") - (ior:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) (not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) - (clobber (match_scratch:VM 4 "=X,X,X,r"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") + (ior:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) + (not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) + (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) + (clobber (match_scratch:VM 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ vnand %3,%1,%0\;vorc %3,%3,%2 - vnand %0,%1,%0\;vorc %0,%0,%2 - vnand %1,%1,%0\;vorc %1,%1,%2 + vnand %3,%1,%0\;vorc %3,%3,%2 + vnand %3,%1,%0\;vorc %3,%3,%2 vnand %4,%1,%0\;vorc %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: vector outer: orc op vorc rtl ior inv 0 comp 1 -;; inner: nor op vnor rtl and inv 0 comp 3 +;; vector vnor -> vorc (define_insn "*fuse_vnor_vorc" - [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v") - (ior:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) (not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) - (clobber (match_scratch:VM 4 "=X,X,X,r"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") + (ior:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) + (not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) + (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) + (clobber (match_scratch:VM 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ vnor %3,%1,%0\;vorc %3,%3,%2 - vnor %0,%1,%0\;vorc %0,%0,%2 - vnor %1,%1,%0\;vorc %1,%1,%2 + vnor %3,%1,%0\;vorc %3,%3,%2 + vnor %3,%1,%0\;vorc %3,%3,%2 vnor %4,%1,%0\;vorc %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: vector outer: orc op vorc rtl ior inv 0 comp 1 -;; inner: or op vor rtl ior inv 0 comp 0 +;; vector vor -> vorc (define_insn "*fuse_vor_vorc" - [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v") - (ior:VM (ior:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) - (clobber (match_scratch:VM 4 "=X,X,X,r"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") + (ior:VM (ior:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") + (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) + (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) + (clobber (match_scratch:VM 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ vor %3,%1,%0\;vorc %3,%3,%2 - vor %0,%1,%0\;vorc %0,%0,%2 - vor %1,%1,%0\;vorc %1,%1,%2 + vor %3,%1,%0\;vorc %3,%3,%2 + vor %3,%1,%0\;vorc %3,%3,%2 vor %4,%1,%0\;vorc %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: vector outer: orc op vorc rtl ior inv 0 comp 1 -;; inner: orc op vorc rtl ior inv 0 comp 1 +;; vector vorc -> vorc (define_insn "*fuse_vorc_vorc" - [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v") - (ior:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) - (clobber (match_scratch:VM 4 "=X,X,X,r"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") + (ior:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) + (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) + (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) + (clobber (match_scratch:VM 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ vorc %3,%1,%0\;vorc %3,%3,%2 - vorc %0,%1,%0\;vorc %0,%0,%2 - vorc %1,%1,%0\;vorc %1,%1,%2 + vorc %3,%1,%0\;vorc %3,%3,%2 + vorc %3,%1,%0\;vorc %3,%3,%2 vorc %4,%1,%0\;vorc %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: vector outer: orc op vorc rtl ior inv 0 comp 1 -;; inner: xor op vxor rtl xor inv 0 comp 0 +;; vector vxor -> vorc (define_insn "*fuse_vxor_vorc" - [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v") - (ior:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) - (clobber (match_scratch:VM 4 "=X,X,X,r"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") + (ior:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") + (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) + (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) + (clobber (match_scratch:VM 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ vxor %3,%1,%0\;vorc %3,%3,%2 - vxor %0,%1,%0\;vorc %0,%0,%2 - vxor %1,%1,%0\;vorc %1,%1,%2 + vxor %3,%1,%0\;vorc %3,%3,%2 + vxor %3,%1,%0\;vorc %3,%3,%2 vxor %4,%1,%0\;vorc %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: vector outer: xor op vxor rtl xor inv 0 comp 0 -;; inner: and op vand rtl and inv 0 comp 0 +;; vector vand -> vxor (define_insn "*fuse_vand_vxor" - [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v") - (xor:VM (and:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) - (clobber (match_scratch:VM 4 "=X,X,X,r"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") + (xor:VM (and:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") + (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) + (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) + (clobber (match_scratch:VM 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ vand %3,%1,%0\;vxor %3,%3,%2 - vand %0,%1,%0\;vxor %0,%0,%2 - vand %1,%1,%0\;vxor %1,%1,%2 + vand %3,%1,%0\;vxor %3,%3,%2 + vand %3,%1,%0\;vxor %3,%3,%2 vand %4,%1,%0\;vxor %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: vector outer: xor op vxor rtl xor inv 0 comp 0 -;; inner: andc op vandc rtl and inv 0 comp 1 +;; vector vandc -> vxor (define_insn "*fuse_vandc_vxor" - [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v") - (xor:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) - (clobber (match_scratch:VM 4 "=X,X,X,r"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") + (xor:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) + (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) + (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) + (clobber (match_scratch:VM 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ vandc %3,%1,%0\;vxor %3,%3,%2 - vandc %0,%1,%0\;vxor %0,%0,%2 - vandc %1,%1,%0\;vxor %1,%1,%2 + vandc %3,%1,%0\;vxor %3,%3,%2 + vandc %3,%1,%0\;vxor %3,%3,%2 vandc %4,%1,%0\;vxor %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: vector outer: xor op vxor rtl xor inv 0 comp 0 -;; inner: eqv op veqv rtl xor inv 1 comp 0 +;; vector veqv -> vxor (define_insn "*fuse_veqv_vxor" - [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v") - (xor:VM (not:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) - (clobber (match_scratch:VM 4 "=X,X,X,r"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") + (xor:VM (not:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") + (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) + (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) + (clobber (match_scratch:VM 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ veqv %3,%1,%0\;vxor %3,%3,%2 - veqv %0,%1,%0\;vxor %0,%0,%2 - veqv %1,%1,%0\;vxor %1,%1,%2 + veqv %3,%1,%0\;vxor %3,%3,%2 + veqv %3,%1,%0\;vxor %3,%3,%2 veqv %4,%1,%0\;vxor %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: vector outer: xor op vxor rtl xor inv 0 comp 0 -;; inner: nand op vnand rtl ior inv 0 comp 3 +;; vector vnand -> vxor (define_insn "*fuse_vnand_vxor" - [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v") - (xor:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) (not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) - (clobber (match_scratch:VM 4 "=X,X,X,r"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") + (xor:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) + (not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) + (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) + (clobber (match_scratch:VM 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ vnand %3,%1,%0\;vxor %3,%3,%2 - vnand %0,%1,%0\;vxor %0,%0,%2 - vnand %1,%1,%0\;vxor %1,%1,%2 + vnand %3,%1,%0\;vxor %3,%3,%2 + vnand %3,%1,%0\;vxor %3,%3,%2 vnand %4,%1,%0\;vxor %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: vector outer: xor op vxor rtl xor inv 0 comp 0 -;; inner: nor op vnor rtl and inv 0 comp 3 +;; vector vnor -> vxor (define_insn "*fuse_vnor_vxor" - [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v") - (xor:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) (not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) - (clobber (match_scratch:VM 4 "=X,X,X,r"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") + (xor:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) + (not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) + (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) + (clobber (match_scratch:VM 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ vnor %3,%1,%0\;vxor %3,%3,%2 - vnor %0,%1,%0\;vxor %0,%0,%2 - vnor %1,%1,%0\;vxor %1,%1,%2 + vnor %3,%1,%0\;vxor %3,%3,%2 + vnor %3,%1,%0\;vxor %3,%3,%2 vnor %4,%1,%0\;vxor %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: vector outer: xor op vxor rtl xor inv 0 comp 0 -;; inner: or op vor rtl ior inv 0 comp 0 +;; vector vor -> vxor (define_insn "*fuse_vor_vxor" - [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v") - (xor:VM (ior:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) - (clobber (match_scratch:VM 4 "=X,X,X,r"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") + (xor:VM (ior:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") + (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) + (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) + (clobber (match_scratch:VM 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ vor %3,%1,%0\;vxor %3,%3,%2 - vor %0,%1,%0\;vxor %0,%0,%2 - vor %1,%1,%0\;vxor %1,%1,%2 + vor %3,%1,%0\;vxor %3,%3,%2 + vor %3,%1,%0\;vxor %3,%3,%2 vor %4,%1,%0\;vxor %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: vector outer: xor op vxor rtl xor inv 0 comp 0 -;; inner: orc op vorc rtl ior inv 0 comp 1 +;; vector vorc -> vxor (define_insn "*fuse_vorc_vxor" - [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v") - (xor:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) - (clobber (match_scratch:VM 4 "=X,X,X,r"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") + (xor:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) + (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) + (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) + (clobber (match_scratch:VM 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ vorc %3,%1,%0\;vxor %3,%3,%2 - vorc %0,%1,%0\;vxor %0,%0,%2 - vorc %1,%1,%0\;vxor %1,%1,%2 + vorc %3,%1,%0\;vxor %3,%3,%2 + vorc %3,%1,%0\;vxor %3,%3,%2 vorc %4,%1,%0\;vxor %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_2logical -;; kind: vector outer: xor op vxor rtl xor inv 0 comp 0 -;; inner: xor op vxor rtl xor inv 0 comp 0 +;; vector vxor -> vxor (define_insn "*fuse_vxor_vxor" - [(set (match_operand:VM 3 "altivec_register_operand" "=&v,0,1,v") - (xor:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") (match_operand:VM 1 "altivec_register_operand" "%v,v,v,v")) (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) - (clobber (match_scratch:VM 4 "=X,X,X,r"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=0,1,&v,v") + (xor:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") + (match_operand:VM 1 "altivec_register_operand" "%v,v,v,v")) + (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) + (clobber (match_scratch:VM 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ vxor %3,%1,%0\;vxor %3,%3,%2 - vxor %0,%1,%0\;vxor %0,%0,%2 - vxor %1,%1,%0\;vxor %1,%1,%2 + vxor %3,%1,%0\;vxor %3,%3,%2 + vxor %3,%1,%0\;vxor %3,%3,%2 vxor %4,%1,%0\;vxor %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") diff --git a/gcc/config/rs6000/genfusion.pl b/gcc/config/rs6000/genfusion.pl index 837af7ac123..e1c45f57065 100755 --- a/gcc/config/rs6000/genfusion.pl +++ b/gcc/config/rs6000/genfusion.pl @@ -192,7 +192,8 @@ sub gen_2logical if ( ($inner_comp & 2) == 2 ) { $inner_arg1 = "(not:${mode} $inner_arg1)"; } - $inner_exp = "(${inner_rtl}:${mode} ${inner_arg0} ${inner_arg1})"; + $inner_exp = "(${inner_rtl}:${mode} ${inner_arg0} + ${inner_arg1})"; if ( $inner_inv == 1 ) { $inner_exp = "(not:${mode} $inner_exp)"; } @@ -203,7 +204,8 @@ sub gen_2logical if ( ($outer_comp & 2) == 2 ) { $inner_exp = "(not:${mode} $inner_exp)"; } - $outer_exp = "(${outer_rtl}:${mode} ${inner_exp} ${outer_arg2})"; + $outer_exp = "(${outer_rtl}:${mode} ${inner_exp} + ${outer_arg2})"; if ( $outer_inv == 1 ) { $outer_exp = "(not:${mode} $outer_exp)"; } @@ -211,17 +213,16 @@ sub gen_2logical $insn = <<"EOF"; ;; logical-logical fusion pattern generated by gen_2logical -;; kind: $kind outer: $outer op $outer_op rtl $outer_rtl inv $outer_inv comp $outer_comp -;; inner: $inner op $inner_op rtl $inner_rtl inv $inner_inv comp $inner_comp +;; $kind $inner_op -> $outer_op (define_insn "*fuse_${inner_op}_${outer_op}" - [(set (match_operand:${mode} 3 "${pred}" "=&${constraint},0,1,${constraint}") + [(set (match_operand:${mode} 3 "${pred}" "=0,1,&${constraint},${constraint}") ${outer_exp}) - (clobber (match_scratch:${mode} 4 "=X,X,X,r"))] + (clobber (match_scratch:${mode} 4 "=X,X,X,&r"))] "(TARGET_P10_FUSION && TARGET_P10_FUSION_2LOGICAL)" "@ ${inner_op} %3,%1,%0\\;${outer_op} %3,%3,%2 - ${inner_op} %0,%1,%0\\;${outer_op} %0,%0,%2 - ${inner_op} %1,%1,%0\\;${outer_op} %1,%1,%2 + ${inner_op} %3,%1,%0\\;${outer_op} %3,%3,%2 + ${inner_op} %3,%1,%0\\;${outer_op} %3,%3,%2 ${inner_op} %4,%1,%0\\;${outer_op} %3,%4,%2" [(set_attr "type" "logical") (set_attr "cost" "6") -- 2.30.2