From 751a18d7e974123352e372c75bb17226e6fabec0 Mon Sep 17 00:00:00 2001 From: Diego H Date: Thu, 12 Dec 2019 17:32:58 -0600 Subject: [PATCH] Fixing citation in xc7_xcu_brams.txt file. Fixing RAMB36E1 test. --- techlibs/xilinx/xc7_xcu_brams.txt | 10 +++++----- tests/arch/xilinx/memory_params.ys | 4 ++-- 2 files changed, 7 insertions(+), 7 deletions(-) diff --git a/techlibs/xilinx/xc7_xcu_brams.txt b/techlibs/xilinx/xc7_xcu_brams.txt index 87e659bbc..b7c893ff7 100644 --- a/techlibs/xilinx/xc7_xcu_brams.txt +++ b/techlibs/xilinx/xc7_xcu_brams.txt @@ -1,4 +1,3 @@ - bram $__XILINX_RAMB36_SDP init 1 abits 9 @@ -72,6 +71,11 @@ bram $__XILINX_RAMB18_TDP clkpol 2 3 endbram +# The "min bits" value were taken from: +# [[CITE]] 7 Series FPGAs Memory Resources User Guide (UG473), +# v1.14 ed., p 29-30, July, 2019. +# https://www.xilinx.com/support/documentation/user_guides/ug473_7Series_Memory_Resources.pdf + match $__XILINX_RAMB36_SDP min bits 1024 min efficiency 5 @@ -102,7 +106,3 @@ match $__XILINX_RAMB18_TDP shuffle_enable B make_transp endmatch - -# [[CITE]] 7 Series FPGAs Memory Resources User Guide (UG473), -# v1.14 ed., p 29-30, July, 2019. - diff --git a/tests/arch/xilinx/memory_params.ys b/tests/arch/xilinx/memory_params.ys index 657629e0f..c1b0ca489 100644 --- a/tests/arch/xilinx/memory_params.ys +++ b/tests/arch/xilinx/memory_params.ys @@ -37,10 +37,10 @@ cd sync_ram_sdp select -assert-count 0 t:RAMB18E1 select -assert-count 4 t:RAM128X1D -# More than 18K bits and addr <= 36: -> RAMB36E1 +# More than 18K bits, data width <= 36 (TDP), and address width from 10 to 15b (non-cascaded) -> RAMB36E1 design -reset read_verilog ../common/memory_params.v -chparam -set ADDRESS_WIDTH 15 -set DATA_WIDTH 1 sync_ram_sdp +chparam -set ADDRESS_WIDTH 10 -set DATA_WIDTH 36 sync_ram_sdp synth_xilinx -top sync_ram_sdp cd sync_ram_sdp select -assert-count 1 t:RAMB36E1 -- 2.30.2