From 751a88c450b3737b761009b8c42db0a5db825881 Mon Sep 17 00:00:00 2001 From: Jacob Lifshay Date: Mon, 6 Nov 2023 20:37:07 -0800 Subject: [PATCH] support TRAP being called without setting a trap_bit --- src/openpower/decoder/isa/caller.py | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/openpower/decoder/isa/caller.py b/src/openpower/decoder/isa/caller.py index 7f547815..0c5199e2 100644 --- a/src/openpower/decoder/isa/caller.py +++ b/src/openpower/decoder/isa/caller.py @@ -1372,7 +1372,8 @@ class ISACaller(ISACallerHelper, ISAFPHelpers, StepLoop): if self.is_svp64_mode: self.spr['SVSRR0'] = self.namespace['SVSTATE'].value self.trap_nia = SelectableInt(trap_addr | (kaivb & ~0x1fff), 64) - self.spr['SRR1'][trap_bit] = 1 # change *copy* of MSR in SRR1 + if trap_bit is not None: + self.spr['SRR1'][trap_bit] = 1 # change *copy* of MSR in SRR1 # set exception bits. TODO: this should, based on the address # in figure 66 p1065 V3.0B and the table figure 65 p1063 set these -- 2.30.2