From 752e34058d0cbcfab4f2ac3ed3c00864059ca185 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Mon, 29 Oct 2018 01:50:15 +0000 Subject: [PATCH] redirect READ_REG to add addr_mode --- riscv/sv_insn_redirect.cc | 6 ++++-- riscv/sv_insn_redirect.h | 5 ++++- 2 files changed, 8 insertions(+), 3 deletions(-) diff --git a/riscv/sv_insn_redirect.cc b/riscv/sv_insn_redirect.cc index 59268bf..3e8f389 100644 --- a/riscv/sv_insn_redirect.cc +++ b/riscv/sv_insn_redirect.cc @@ -145,7 +145,8 @@ freg_t (sv_proc_t::READ_FREG)(reg_spec_t const& spec) return _insn->p->get_state()->FPR[reg]; // XXX TODO: offset } -reg_t (sv_proc_t::READ_REG)(reg_spec_t const& spec) +reg_t sv_proc_t::READ_REG(reg_spec_t const& spec, sv_reg_t const& imm, + bool addr_mode, size_t width) { reg_t reg = spec.reg; int bitwidth = get_bitwidth(_insn->reg_elwidth(reg, true), xlen); @@ -929,7 +930,8 @@ sv_float128_t sv_proc_t::f64_to_f128( sv_float64_t a) sv_reg_t sv_proc_t::mmu_load(reg_spec_t const& spec, sv_reg_t const& offs, size_t width, bool ext) { - reg_t reg = READ_REG(spec); + // okaay, so a different "mode" applies, here + reg_t reg = READ_REG(spec, true, offs, width); sv_reg_t addr = rv_add(reg, offs); switch (width) { diff --git a/riscv/sv_insn_redirect.h b/riscv/sv_insn_redirect.h index 76a22d4..4cd2bb2 100644 --- a/riscv/sv_insn_redirect.h +++ b/riscv/sv_insn_redirect.h @@ -85,7 +85,10 @@ public: void (WRITE_FRD)(sv_float128_t value); void (WRITE_FRD)(sv_float64_t value); void (WRITE_FRD)(sv_float32_t value); - reg_t (READ_REG)(reg_spec_t const& i); + reg_t READ_REG(reg_spec_t const& i, sv_reg_t const& imm, + bool addr_mode, size_t width); + reg_t READ_REG(reg_spec_t const& spec) + { return READ_REG(spec, sv_reg_t(0), false, xlen); } freg_t (READ_FREG)(reg_spec_t const& i); processor_t *p; -- 2.30.2