From 7542087cb5943c9cede326576b7c9343d91bc4e6 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Thu, 1 Apr 2021 13:23:58 +0100 Subject: [PATCH] disable PLL for litex build, new variant --- libresoc/core.py | 3 ++- ls180soc.py | 17 +++++++++-------- 2 files changed, 11 insertions(+), 9 deletions(-) diff --git a/libresoc/core.py b/libresoc/core.py index 3340a0c..d7ed1e7 100644 --- a/libresoc/core.py +++ b/libresoc/core.py @@ -15,6 +15,7 @@ from litex.build.generic_platform import ConstraintManager CPU_VARIANTS = ["standard", "standard32", "standardjtag", "standardjtagtestgpio", "ls180", "ls180sram4k", + "ls180nopll", "standardjtagnoirq"] @@ -269,7 +270,7 @@ class LibreSoC(CPU): )) # add clock select, pll output - if "ls180" in variant: + if "ls180" in variant and "pll" not in variant: self.pll_18_o = Signal() self.clk_sel = Signal(2) self.pll_lck_o = Signal() diff --git a/ls180soc.py b/ls180soc.py index 44a4ce8..9821038 100755 --- a/ls180soc.py +++ b/ls180soc.py @@ -315,7 +315,7 @@ class LibreSoCSim(SoCCore): #cpu_data_width = 32 cpu_data_width = 64 - variant = "ls180" + variant = "ls180nopll" # reserve XICS ICP and XICS memory addresses. self.mem_map['icp'] = 0xc0010000 @@ -418,14 +418,15 @@ class LibreSoCSim(SoCCore): self.submodules.crg = CRG(platform.request("sys_clk"), platform.request("sys_rst")) - # PLL/Clock Select - clksel_i = platform.request("sys_clksel_i") - pll18_o = platform.request("sys_pll_18_o") - pll_lck_o = platform.request("sys_pll_lck_o") + if hasattr(self.cpu, "clk_sel"): + # PLL/Clock Select + clksel_i = platform.request("sys_clksel_i") + pll18_o = platform.request("sys_pll_18_o") + pll_lck_o = platform.request("sys_pll_lck_o") - self.comb += self.cpu.clk_sel.eq(clksel_i) # allow clock src select - self.comb += pll18_o.eq(self.cpu.pll_18_o) # "test feed" from the PLL - self.comb += pll_lck_o.eq(self.cpu.pll_lck_o) # PLL lock flag + self.comb += self.cpu.clk_sel.eq(clksel_i) # allow clock src select + self.comb += pll18_o.eq(self.cpu.pll_18_o) # "test feed" from PLL + self.comb += pll_lck_o.eq(self.cpu.pll_lck_o) # PLL lock flag #ram_init = [] -- 2.30.2