From 75771552d186c50128ae8fe2050204cfc9e470f4 Mon Sep 17 00:00:00 2001 From: lkcl Date: Sat, 19 Dec 2020 23:18:09 +0000 Subject: [PATCH] --- openpower/sv/svp_rewrite/svp64.mdwn | 1 + 1 file changed, 1 insertion(+) diff --git a/openpower/sv/svp_rewrite/svp64.mdwn b/openpower/sv/svp_rewrite/svp64.mdwn index 41593b5c2..c8dfc1a9e 100644 --- a/openpower/sv/svp_rewrite/svp64.mdwn +++ b/openpower/sv/svp_rewrite/svp64.mdwn @@ -495,6 +495,7 @@ to 4-bit CR fields. Vectorised Integer results, when Rc=1, will begin writing to CR8 (TBD evaluate) and increase sequentially from there. Vectorised FP results, when Rc=1, start from CR32 (TBD evaluate). This is so that: +* implementations may rely on the Vector CRs being aligned to 8. This means that CRs may be read or written in aligned batches of 32 bits, for high performance implementations. * scalar Rc=1 operation (CR0, CR1) and callee-saved CRs (CR2-4) are not overwritten by vector Rc=1 operations except for very large VL * Vector FP and Integer Rc=1 operations do not overwrite each other except for large VL. -- 2.30.2