From 7592c8bcecb16c427858cf11c9c7fa835017998c Mon Sep 17 00:00:00 2001 From: Cesar Strauss Date: Sun, 20 Dec 2020 11:18:34 -0300 Subject: [PATCH] Add support for CXXSim simulation --- src/soc/bus/test/test_sram_wishbone.py | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/src/soc/bus/test/test_sram_wishbone.py b/src/soc/bus/test/test_sram_wishbone.py index d1a6d63a..05ecc202 100644 --- a/src/soc/bus/test/test_sram_wishbone.py +++ b/src/soc/bus/test/test_sram_wishbone.py @@ -5,6 +5,10 @@ Bugs: from nmigen_soc.wishbone.sram import SRAM from nmigen import Memory, Signal, Module +# NOTE: to use cxxsim, export NMIGEN_SIM_MODE=cxxsim from the shell +# Also, check out the cxxsim nmigen branch, and latest yosys from git +from nmutil.sim_tmp_alternative import Simulator, Settle + memory = Memory(width=64, depth=16) sram = SRAM(memory=memory, granularity=16) @@ -19,7 +23,6 @@ sram = SRAM(memory=memory, granularity=16) # sram.bus.ack # setup simulation -from nmigen.back.pysim import Simulator, Delay, Settle m = Module() m.submodules.sram = sram sim = Simulator(m) -- 2.30.2