From 759858f7398094f26a89be802e942c9da021c55f Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Sun, 26 May 2013 18:07:26 +0200 Subject: [PATCH] Use migen.fhdl.std --- README | 3 +-- mibuild/crg.py | 3 +-- mibuild/generic_platform.py | 2 +- mibuild/xilinx_ise.py | 5 ++--- 4 files changed, 5 insertions(+), 8 deletions(-) diff --git a/README b/README index 09e29e1d..d649b4b1 100644 --- a/README +++ b/README @@ -3,8 +3,7 @@ Mibuild (Milkymist Build system) Quick intro: -from migen.fhdl.structure import * -from migen.fhdl.module import Module +from migen.fhdl.std import * from mibuild.platforms import m1 plat = m1.Platform() led = plat.request("user_led") diff --git a/mibuild/crg.py b/mibuild/crg.py index 7b5799f3..5d51a13b 100644 --- a/mibuild/crg.py +++ b/mibuild/crg.py @@ -1,5 +1,4 @@ -from migen.fhdl.structure import * -from migen.fhdl.module import Module +from migen.fhdl.std import * class SimpleCRG(Module): def __init__(self, platform, clk_name, rst_name, rst_invert=False): diff --git a/mibuild/generic_platform.py b/mibuild/generic_platform.py index 3ff2f02e..2ce4673b 100644 --- a/mibuild/generic_platform.py +++ b/mibuild/generic_platform.py @@ -1,7 +1,7 @@ from copy import copy import os, argparse -from migen.fhdl.structure import * +from migen.fhdl.std import * from migen.genlib.record import Record from migen.fhdl import verilog diff --git a/mibuild/xilinx_ise.py b/mibuild/xilinx_ise.py index d6ac4729..c5273cab 100644 --- a/mibuild/xilinx_ise.py +++ b/mibuild/xilinx_ise.py @@ -1,9 +1,8 @@ import os, struct, subprocess, sys from decimal import Decimal -from migen.fhdl.structure import * -from migen.fhdl.specials import Instance, SynthesisDirective -from migen.fhdl.module import Module +from migen.fhdl.std import * +from migen.fhdl.specials import SynthesisDirective from migen.genlib.cdc import * from mibuild.generic_platform import * -- 2.30.2