From 75b33aa23b71c2133321ad220e4a01f7115d95b3 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sat, 17 Sep 2022 20:48:57 +0100 Subject: [PATCH] add zz mode to sv/trans/svp64.py as a hack --- src/openpower/consts.py | 1 + src/openpower/sv/trans/svp64.py | 8 +++++--- 2 files changed, 6 insertions(+), 3 deletions(-) diff --git a/src/openpower/consts.py b/src/openpower/consts.py index 65f2bc08..3a5e2c8e 100644 --- a/src/openpower/consts.py +++ b/src/openpower/consts.py @@ -248,6 +248,7 @@ class SVP64MODEb(_Const): # when predicate not set: 0=ignore/skip 1=zero DZ = 3 # for destination SZ = 4 # for source + ZZ = 3 # for both sz/dz, on all but CR-ops # for branch-conditional BC_SNZ = 3 # for branch-conditional mode BC_VLI = 2 # for VL include/exclude on VLSET mode diff --git a/src/openpower/sv/trans/svp64.py b/src/openpower/sv/trans/svp64.py index bd5f9b76..c617375a 100644 --- a/src/openpower/sv/trans/svp64.py +++ b/src/openpower/sv/trans/svp64.py @@ -1107,6 +1107,8 @@ class SVP64Asm: sv_mode = 0b10 saturation = 0 # predicate zeroing + elif encmode == 'zz': # TODO, a lot more checking on legality + dst_zero = 1 # NOT on cr_ops, that's RM[6] elif encmode == 'sz': src_zero = 1 elif encmode == 'dz': @@ -1235,11 +1237,11 @@ class SVP64Asm: """ | 0-1 | 2 | 3 4 | description | | --- | --- |---------|--------------------------- | - | 00 | 0 | dz els | normal mode | - | 00 | 1 | dz shf | shift mode | + | 00 | 0 | zz els | normal mode | + | 00 | 1 | / / | reserved | | 01 | inv | CR-bit | Rc=1: ffirst CR sel | | 01 | inv | els RC1 | Rc=0: ffirst z/nonz | - | 10 | N | dz els | sat mode: N=0/1 u/s | + | 10 | N | zz els | sat mode: N=0/1 u/s | | 11 | inv | CR-bit | Rc=1: pred-result CR sel | | 11 | inv | els RC1 | Rc=0: pred-result z/nonz | """ -- 2.30.2