From 75d25af3aae4788570ed602ed11328c63c3a1a54 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Sun, 10 Nov 2013 16:12:24 +0100 Subject: [PATCH] cosmetic changes --- misoclib/s6ddrphy/__init__.py | 12 +++++++----- software/common.mak | 2 +- 2 files changed, 8 insertions(+), 6 deletions(-) diff --git a/misoclib/s6ddrphy/__init__.py b/misoclib/s6ddrphy/__init__.py index c66b025b..044c0afc 100644 --- a/misoclib/s6ddrphy/__init__.py +++ b/misoclib/s6ddrphy/__init__.py @@ -56,9 +56,9 @@ class S6DDRPHY(Module): ### # sys_clk : system clk, used for dfi interface - # sdram_half_clk : half rate sdram clk + # sdram_half_clk : half rate sdram clk # sdram_full_wr_clk : full rate sdram write clk - # sdram_full_rd_clk : full rate sdram write clk + # sdram_full_rd_clk : full rate sdram read clk sd_sys = getattr(self.sync, "sys") sd_sdram_half = getattr(self.sync, "sdram_half") @@ -80,8 +80,11 @@ class S6DDRPHY(Module): sys_clk_d = Signal() sd_sdram_half += [ - If(sys_clk & ~sys_clk_d, phase_sel.eq(0) - ).Else(phase_sel.eq(phase_sel+1)), + If(sys_clk & ~sys_clk_d, + phase_sel.eq(0) + ).Else( + phase_sel.eq(phase_sel+1) + ), sys_clk_d.eq(sys_clk) ] @@ -287,7 +290,6 @@ class S6DDRPHY(Module): o_Q2=d_dfi[0*nphases+0].rddata[i], o_Q3=d_dfi[0*nphases+1].rddata[i+d], o_Q4=d_dfi[0*nphases+1].rddata[i], - ) # Data buffer diff --git a/software/common.mak b/software/common.mak index e5d8d135..7320685e 100644 --- a/software/common.mak +++ b/software/common.mak @@ -18,7 +18,7 @@ LD_quiet = @echo " LD " $@ && $(TARGET_PREFIX)ld OBJCOPY_quiet = @echo " OBJCOPY " $@ && $(TARGET_PREFIX)objcopy RANLIB_quiet = @echo " RANLIB " $@ && $(TARGET_PREFIX)ranlib -GIT_ID:=$(shell python3 -c "from misoclib.identifier.git import get_id; print(hex(get_id()), end='')") +GIT_ID := $(shell python3 -c "from misoclib.identifier.git import get_id; print(hex(get_id()), end='')") ifeq ($(V),1) CC = $(CC_normal) -- 2.30.2