From 75da74cbb6622a1a91d8bdef2a799db766442889 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sun, 29 Apr 2018 15:44:33 +0100 Subject: [PATCH] add mvendor/march WARL update --- isa_conflict_resolution.mdwn | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/isa_conflict_resolution.mdwn b/isa_conflict_resolution.mdwn index 6e02d67c7..baa2f8371 100644 --- a/isa_conflict_resolution.mdwn +++ b/isa_conflict_resolution.mdwn @@ -267,7 +267,7 @@ turn the custom instruction into an actual binary-encoding (plus binary-encoding of the context-switching information). (**TBD, Jacob, separate page? review this para?**) -# mvendorid/marchid WARL +# mvendorid/marchid WARL (Summary: the only idea that meets the full requirements. Needs toolchain backup, but only when the first chip is released) @@ -358,7 +358,7 @@ Update 29apr2018: hardware-level ISA support to not be permitted to receive RISC-V Certification Compliance. -# ioctl-like +# ioctl-like (Summary: good solid orthogonal idea. See [[ioctl]] for full details) -- 2.30.2