From 75ea36861974a532dd4143226bff6f344458f929 Mon Sep 17 00:00:00 2001 From: lkcl Date: Fri, 8 May 2020 12:01:12 +0100 Subject: [PATCH] --- 180nm_Oct2020.mdwn | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/180nm_Oct2020.mdwn b/180nm_Oct2020.mdwn index 31c187a0a..27417ece8 100644 --- a/180nm_Oct2020.mdwn +++ b/180nm_Oct2020.mdwn @@ -19,7 +19,7 @@ To be expanded with links to bugreports * a very very basic Common Data Bus infrastructure. * a TLB and MMU are not strictly essential (not for a proof-of-concept ASIC) * neither in some ways is a L1 cache -* interfaces we need as a bare minimum include GPIO, EINT, SPI and QSPI, +* [[180nm_oct2020/interfaces]] we need as a bare minimum include GPIO, EINT, SPI and QSPI, I2C, UART16550, LPC (from Raptor Engineering) and that actually might even be it. -- 2.30.2