From 760284033d6f255790d44bfcda0d1625a0c7bc87 Mon Sep 17 00:00:00 2001
From: =?utf8?q?Marcelina=20Ko=C5=9Bcielnicka?= <mwk@0x04.net>
Date: Sat, 6 Mar 2021 03:59:03 +0100
Subject: [PATCH] proc_dff: Fix emitted FF when a register is not assigned in
 async reset

Fixes #2619.
---
 passes/proc/proc_dff.cc |  4 ++++
 tests/proc/bug2619.ys   | 23 +++++++++++++++++++++++
 2 files changed, 27 insertions(+)
 create mode 100644 tests/proc/bug2619.ys

diff --git a/passes/proc/proc_dff.cc b/passes/proc/proc_dff.cc
index e320a72a6..2b6ca8449 100644
--- a/passes/proc/proc_dff.cc
+++ b/passes/proc/proc_dff.cc
@@ -328,6 +328,10 @@ void proc_dff(RTLIL::Module *mod, RTLIL::Process *proc, ConstEval &ce)
 		ce.assign_map.apply(sig);
 
 		if (rstval == sig) {
+			if (sync_level->type == RTLIL::SyncType::ST1)
+				insig = mod->Mux(NEW_ID, insig, sig, sync_level->signal);
+			else
+				insig = mod->Mux(NEW_ID, sig, insig, sync_level->signal);
 			rstval = RTLIL::SigSpec(RTLIL::State::Sz, sig.size());
 			sync_level = NULL;
 		}
diff --git a/tests/proc/bug2619.ys b/tests/proc/bug2619.ys
new file mode 100644
index 000000000..a080b94f5
--- /dev/null
+++ b/tests/proc/bug2619.ys
@@ -0,0 +1,23 @@
+read_verilog << EOT
+
+module top(...);
+
+input D1, D2, R, CLK;
+output reg Q1, Q2;
+
+always @(posedge CLK, posedge R) begin
+	Q1 <= 0;
+	if (!R) begin
+		Q1 <= D1;
+		Q2 <= D2;
+	end
+end
+
+endmodule
+
+EOT
+
+proc
+opt
+select -assert-count 1 t:$adff
+select -assert-count 1 t:$dffe
-- 
2.30.2