From 7610b5f37bfb71b630cfaba9c1eb278461cacb60 Mon Sep 17 00:00:00 2001 From: Tobias Platen Date: Mon, 13 Dec 2021 14:27:51 +0100 Subject: [PATCH] update old TestMicrowattMemoryPortInterface --- src/soc/experiment/test/test_mmu_dcache_pi.py | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/soc/experiment/test/test_mmu_dcache_pi.py b/src/soc/experiment/test/test_mmu_dcache_pi.py index a4ad1dab..c2b76df5 100644 --- a/src/soc/experiment/test/test_mmu_dcache_pi.py +++ b/src/soc/experiment/test/test_mmu_dcache_pi.py @@ -85,18 +85,18 @@ class TestMicrowattMemoryPortInterface(PortInterfaceBase): self.mmu = mmu self.dcache = dcache - def set_wr_addr(self, m, addr, mask, misalign, msr_pr, is_dcbz): + def set_wr_addr(self, m, addr, mask, misalign, msr, is_dcbz): m.d.comb += self.dcache.d_in.addr.eq(addr) m.d.comb += self.mmu.l_in.addr.eq(addr) m.d.comb += self.mmu.l_in.load.eq(0) - m.d.comb += self.mmu.l_in.priv.eq(1) # TODO put msr_pr here + m.d.comb += self.mmu.l_in.priv.eq(~msr.pr) # TODO verify m.d.comb += self.mmu.l_in.valid.eq(1) - def set_rd_addr(self, m, addr, mask, misalign, msr_pr): + def set_rd_addr(self, m, addr, mask, misalign, msr): m.d.comb += self.dcache.d_in.addr.eq(addr) m.d.comb += self.mmu.l_in.addr.eq(addr) m.d.comb += self.mmu.l_in.load.eq(1) - m.d.comb += self.mmu.l_in.priv.eq(1) # TODO put msr_pr here + m.d.comb += self.mmu.l_in.priv.eq(~msr.pr) # TODO verify m.d.comb += self.mmu.l_in.valid.eq(1) def set_wr_data(self, m, data, wen): -- 2.30.2