From 763d0d8086f14ada1cefa44e171c17eaf9fd95ce Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sat, 14 Apr 2018 07:38:04 +0100 Subject: [PATCH] add commentary --- simple_v_extension.mdwn | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/simple_v_extension.mdwn b/simple_v_extension.mdwn index 996ec164b..e1715844d 100644 --- a/simple_v_extension.mdwn +++ b/simple_v_extension.mdwn @@ -1076,6 +1076,17 @@ Virtual Register Reordering: | r4 | (32..0) | (32..0) | (32..0) | | r7 | (32..0) | +SIMD register file splitting still to consider. For RV64, benefits of doubling +(quadrupling in the case of Half-Precision IEEE754 FP) the apparent +size of the floating point register file to 64 (128 in the case of HP) +seem pretty clear and worth the complexity. + +64 virtual 32-bit F.P. registers and given that 32-bit FP operations are +done on 64-bit registers it's not so conceptually difficult.  May even +be achieved by *actually* splitting the regfile into 64 virtual 32-bit +registers such that a 64-bit FP scalar operation is dropped into (r0.H +r0.L) tuples.  Implementation therefore hidden through register renaming. + # Analysis of CSR decoding on latency It could indeed have been logically deduced (or expected), that there -- 2.30.2