From 766647dda1fd2747b2fa867d0aad428bfad72e7c Mon Sep 17 00:00:00 2001 From: Daniel Benusovich Date: Sun, 21 Apr 2019 16:36:04 -0700 Subject: [PATCH] Remove LRU bits from memory --- TLB/src/SetAssociativeCache.py | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/TLB/src/SetAssociativeCache.py b/TLB/src/SetAssociativeCache.py index 25ee1b7c..b91d6d69 100644 --- a/TLB/src/SetAssociativeCache.py +++ b/TLB/src/SetAssociativeCache.py @@ -37,9 +37,8 @@ class SetAssociativeCache(): self.data_end = self.data_start + data_size self.tag_start = self.data_end self.tag_end = self.tag_start + tag_size - cache_data = way_count + 1 # Bits required to represent LRU and active input_size = tag_size + data_size # Size of the input data - memory_width = input_size + cache_data # The width of the cache memory + memory_width = input_size + 1 # The width of the cache memory self.memory_array = Array(Memory(memory_width, set_count) for x in range(way_count)) # Memory Array self.way_count = way_count # The number of slots in one set @@ -197,7 +196,6 @@ class SetAssociativeCache(): self.read(m) with m.Case(SA_WR): self.write(m) - # What to do when there is no space # Maybe catch multiple tags write here? # TODO return m -- 2.30.2