From 767499da99d9b8133ab5ee6489ef18c5a0fd1afa Mon Sep 17 00:00:00 2001
From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 9 Jun 2020 23:38:39 +0100
Subject: [PATCH] experimenting with CR/LR/XER etc in qemu

---
 src/soc/simulator/qemu.py     | 16 +++++++++-------
 src/soc/simulator/test_sim.py | 25 ++++++++++++++++++++++---
 2 files changed, 31 insertions(+), 10 deletions(-)

diff --git a/src/soc/simulator/qemu.py b/src/soc/simulator/qemu.py
index d45c17c8..3c4733a0 100644
--- a/src/soc/simulator/qemu.py
+++ b/src/soc/simulator/qemu.py
@@ -40,13 +40,15 @@ class QemuController:
                 return int(x['payload']['register-values'][0]['value'], 0)
         return None
 
-    def get_pc(self): return self._get_register('pc')
-    def get_cr(self): return self._get_register('cnd')
-    def get_xer(self): return self._get_register('xer')
-    def get_msr(self): return self._get_register('msr')
-    def get_lr(self): return self._get_register('lr')
-    def get_fpscr(self): return self._get_register('fpscr')
-    def get_ctr(self): return self._get_register('cnt') # probably
+    # TODO: use -data-list-register-names instead of hardcoding the values
+    def get_pc(self): return self._get_register('x 64')
+    def get_msr(self): return self._get_register('x 65')
+    def get_cr(self): return self._get_register('x 66')
+    def get_lr(self): return self._get_register('x 67')
+    def get_ctr(self): return self._get_register('x 68') # probably
+    def get_xer(self): return self._get_register('x 69')
+    def get_fpscr(self): return self._get_register('x 70')
+    def get_mq(self): return self._get_register('x 71')
 
     def get_register(self, num):
         return self._get_register('x {}'.format(num))
diff --git a/src/soc/simulator/test_sim.py b/src/soc/simulator/test_sim.py
index ecf04246..9d00476d 100644
--- a/src/soc/simulator/test_sim.py
+++ b/src/soc/simulator/test_sim.py
@@ -61,6 +61,15 @@ class DecoderTestCase(FHDLTestCase):
 
         return simulator
 
+    def test_0_cmp(self):
+        lst = ["addi 6, 0, 0x10",
+               "addi 7, 0, 0x05",
+               "subf. 1, 6, 7",
+               "cmp cr2, 1, 6, 7",
+               ]
+        with Program(lst) as program:
+            self.run_tst_program(program, [1])
+
     def test_example(self):
         lst = ["addi 1, 0, 0x1234",
                "addi 2, 0, 0x5678",
@@ -142,11 +151,21 @@ class DecoderTestCase(FHDLTestCase):
             self.qemu_register_compare(simulator, q, reglist)
         print(simulator.gpr.dump())
 
-
-    def qemu_register_compare(self, simulator, qemu, regs):
+    def qemu_register_compare(self, sim, qemu, regs):
+        qpc, qxer, qcr = qemu.get_pc(), qemu.get_xer(), qemu.get_cr()
+        sim_cr = sim.cr.get_range().value
+        sim_pc = sim.pc.CIA.value
+        sim_xer = sim.spr['XER'].value
+        print("qemu pc", hex(qpc))
+        print("qemu cr", hex(qcr))
+        print("qemu xer", bin(qxer))
+        print("sim pc", sim.pc.CIA.value)
+        print("sim cr", hex(sim_cr))
+        print("sim xer", hex(sim_xer))
+        self.assertEqual(qcr, sim_cr)
         for reg in regs:
             qemu_val = qemu.get_register(reg)
-            sim_val = simulator.gpr(reg).value
+            sim_val = sim.gpr(reg).value
             self.assertEqual(qemu_val, sim_val)
 
 
-- 
2.30.2