From 76835dca95ab9f3f106a0db1e6152ad0740b38b3 Mon Sep 17 00:00:00 2001 From: Dennis Zhang Date: Thu, 22 Oct 2020 01:27:31 +0100 Subject: [PATCH] arm: Auto-vectorization for MVE: vmin/vmax This patch enables MVE vmin/vmax instructions for auto-vectorization. MVE target is included in expander smin3, umin3, smax3 and umax3 for vectorization. Related insns for vmin/vmax in mve.md are modified to use smin, umin, smax and umax expressions instead of unspec to support the expanders. gcc/ChangeLog: 2020-10-22 Dennis Zhang * config/arm/mve.md (mve_vmaxq_): Replace with ... (mve_vmaxq_s, mve_vmaxq_u): ... these new insns to use smax/umax instead of VMAXQ. (mve_vminq_): Replace with ... (mve_vminq_s, mve_vminq_u): ... these new insns to use smin/umin instead of VMINQ. (mve_vmaxnmq_f): Use smax instead of VMAXNMQ_F. (mve_vminnmq_f): Use smin instead of VMINNMQ_F. * config/arm/vec-common.md (smin3): Use the new mode macros ARM_HAVE__ARITH. (umin3, smax3, umax3): Likewise. gcc/testsuite/ChangeLog: * gcc.target/arm/simd/mve-vminmax_1.c: New test. --- gcc/ChangeLog | 14 +++++ gcc/config/arm/mve.md | 50 ++++++++++----- gcc/config/arm/vec-common.md | 26 +++----- gcc/testsuite/ChangeLog | 4 ++ .../gcc.target/arm/simd/mve-vminmax_1.c | 61 +++++++++++++++++++ 5 files changed, 121 insertions(+), 34 deletions(-) create mode 100644 gcc/testsuite/gcc.target/arm/simd/mve-vminmax_1.c diff --git a/gcc/ChangeLog b/gcc/ChangeLog index d6a326cbbc0..59fa1ad4d5d 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,17 @@ +2020-10-22 Dennis Zhang + + * config/arm/mve.md (mve_vmaxq_): Replace with ... + (mve_vmaxq_s, mve_vmaxq_u): ... these new insns to + use smax/umax instead of VMAXQ. + (mve_vminq_): Replace with ... + (mve_vminq_s, mve_vminq_u): ... these new insns to + use smin/umin instead of VMINQ. + (mve_vmaxnmq_f): Use smax instead of VMAXNMQ_F. + (mve_vminnmq_f): Use smin instead of VMINNMQ_F. + * config/arm/vec-common.md (smin3): Use the new mode macros + ARM_HAVE__ARITH. + (umin3, smax3, umax3): Likewise. + 2020-10-22 Dennis Zhang * config/arm/mve.md (mve_vmulq): New entry for vmul instruction diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md index 764e2016316..47c34b9919b 100644 --- a/gcc/config/arm/mve.md +++ b/gcc/config/arm/mve.md @@ -1329,15 +1329,25 @@ ;; ;; [vmaxq_u, vmaxq_s]) ;; -(define_insn "mve_vmaxq_" +(define_insn "mve_vmaxq_s" [ (set (match_operand:MVE_2 0 "s_register_operand" "=w") - (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w") - (match_operand:MVE_2 2 "s_register_operand" "w")] - VMAXQ)) + (smax:MVE_2 (match_operand:MVE_2 1 "s_register_operand" "w") + (match_operand:MVE_2 2 "s_register_operand" "w"))) + ] + "TARGET_HAVE_MVE" + "vmax.%#\t%q0, %q1, %q2" + [(set_attr "type" "mve_move") +]) + +(define_insn "mve_vmaxq_u" + [ + (set (match_operand:MVE_2 0 "s_register_operand" "=w") + (umax:MVE_2 (match_operand:MVE_2 1 "s_register_operand" "w") + (match_operand:MVE_2 2 "s_register_operand" "w"))) ] "TARGET_HAVE_MVE" - "vmax.%#\t%q0, %q1, %q2" + "vmax.%#\t%q0, %q1, %q2" [(set_attr "type" "mve_move") ]) @@ -1389,15 +1399,25 @@ ;; ;; [vminq_s, vminq_u]) ;; -(define_insn "mve_vminq_" +(define_insn "mve_vminq_s" [ (set (match_operand:MVE_2 0 "s_register_operand" "=w") - (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w") - (match_operand:MVE_2 2 "s_register_operand" "w")] - VMINQ)) + (smin:MVE_2 (match_operand:MVE_2 1 "s_register_operand" "w") + (match_operand:MVE_2 2 "s_register_operand" "w"))) ] "TARGET_HAVE_MVE" - "vmin.%#\t%q0, %q1, %q2" + "vmin.%#\t%q0, %q1, %q2" + [(set_attr "type" "mve_move") +]) + +(define_insn "mve_vminq_u" + [ + (set (match_operand:MVE_2 0 "s_register_operand" "=w") + (umin:MVE_2 (match_operand:MVE_2 1 "s_register_operand" "w") + (match_operand:MVE_2 2 "s_register_operand" "w"))) + ] + "TARGET_HAVE_MVE" + "vmin.%#\t%q0, %q1, %q2" [(set_attr "type" "mve_move") ]) @@ -2393,9 +2413,8 @@ (define_insn "mve_vmaxnmq_f" [ (set (match_operand:MVE_0 0 "s_register_operand" "=w") - (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w") - (match_operand:MVE_0 2 "s_register_operand" "w")] - VMAXNMQ_F)) + (smax:MVE_0 (match_operand:MVE_0 1 "s_register_operand" "w") + (match_operand:MVE_0 2 "s_register_operand" "w"))) ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" "vmaxnm.f%# %q0, %q1, %q2" @@ -2453,9 +2472,8 @@ (define_insn "mve_vminnmq_f" [ (set (match_operand:MVE_0 0 "s_register_operand" "=w") - (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w") - (match_operand:MVE_0 2 "s_register_operand" "w")] - VMINNMQ_F)) + (smin:MVE_0 (match_operand:MVE_0 1 "s_register_operand" "w") + (match_operand:MVE_0 2 "s_register_operand" "w"))) ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" "vminnm.f%# %q0, %q1, %q2" diff --git a/gcc/config/arm/vec-common.md b/gcc/config/arm/vec-common.md index 45db60e7411..0f117d6b4ca 100644 --- a/gcc/config/arm/vec-common.md +++ b/gcc/config/arm/vec-common.md @@ -111,39 +111,29 @@ [(set (match_operand:VALLW 0 "s_register_operand") (smin:VALLW (match_operand:VALLW 1 "s_register_operand") (match_operand:VALLW 2 "s_register_operand")))] - "(TARGET_NEON && ((mode != V2SFmode && mode != V4SFmode) - || flag_unsafe_math_optimizations)) - || (TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE (mode))" -{ -}) + "ARM_HAVE__ARITH" +) (define_expand "umin3" [(set (match_operand:VINTW 0 "s_register_operand") (umin:VINTW (match_operand:VINTW 1 "s_register_operand") (match_operand:VINTW 2 "s_register_operand")))] - "TARGET_NEON - || (TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE (mode))" -{ -}) + "ARM_HAVE__ARITH" +) (define_expand "smax3" [(set (match_operand:VALLW 0 "s_register_operand") (smax:VALLW (match_operand:VALLW 1 "s_register_operand") (match_operand:VALLW 2 "s_register_operand")))] - "(TARGET_NEON && ((mode != V2SFmode && mode != V4SFmode) - || flag_unsafe_math_optimizations)) - || (TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE (mode))" -{ -}) + "ARM_HAVE__ARITH" +) (define_expand "umax3" [(set (match_operand:VINTW 0 "s_register_operand") (umax:VINTW (match_operand:VINTW 1 "s_register_operand") (match_operand:VINTW 2 "s_register_operand")))] - "TARGET_NEON - || (TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE (mode))" -{ -}) + "ARM_HAVE__ARITH" +) (define_expand "vec_perm" [(match_operand:VE 0 "s_register_operand") diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index eb55a64b8f8..304d44c9de6 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,7 @@ +2020-10-22 Dennis Zhang + + * gcc.target/arm/simd/mve-vminmax_1.c: New test. + 2020-10-22 Dennis Zhang * gcc.target/arm/simd/mve-vmul_1.c: New test. diff --git a/gcc/testsuite/gcc.target/arm/simd/mve-vminmax_1.c b/gcc/testsuite/gcc.target/arm/simd/mve-vminmax_1.c new file mode 100644 index 00000000000..6c8e7d42906 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/mve-vminmax_1.c @@ -0,0 +1,61 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-options "-O3" } */ +/* { dg-add-options arm_v8_1m_mve } */ + +#include + +#define MAX(a, b) ((a) > (b)) ? (a) : (b) +#define MIN(a, b) ((a) < (b)) ? (a) : (b) + + +#define TEST_BINOP(OP, TY, N) \ + TY test_##OP##_##TY (TY * dest, TY * a, TY * b) \ + { \ + int i; \ + for (i=0; i