From 76851d5bc1ae2544821ba03ae248c22192cce93b Mon Sep 17 00:00:00 2001 From: Cesar Strauss Date: Sat, 13 Feb 2021 16:55:39 -0300 Subject: [PATCH] Check the PC value at the end of each instruction Useful for checking that the PC really points to the next instruction, after fetching a prefixed instruction. --- src/soc/simple/test/test_core.py | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/src/soc/simple/test/test_core.py b/src/soc/simple/test/test_core.py index 271d7064..98d42840 100644 --- a/src/soc/simple/test/test_core.py +++ b/src/soc/simple/test/test_core.py @@ -172,6 +172,12 @@ def check_regs(dut, sim, core, test, code): dut.assertEqual(e_ov, ov, "ov mismatch %s" % (repr(code))) dut.assertEqual(e_ca, ca, "ca mismatch %s" % (repr(code))) + # Check the PC as well + state = core.regs.rf['state'] + pc = yield state.r_ports['cia'].data_o + e_pc = sim.pc.CIA.value + dut.assertEqual(e_pc, pc) + def wait_for_busy_hi(cu): while True: -- 2.30.2