From 768b9e05c96d9aede624f2c79af3409cc7cf7571 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Tue, 21 Dec 2021 15:46:32 +0000 Subject: [PATCH] take a copy of the wb_get memory and then for each unit test overwrite it (resetting) if any unit test has a replacement memory --- src/openpower/decoder/power_decoder2.py | 2 +- src/openpower/test/runner.py | 15 +++++++++++---- 2 files changed, 12 insertions(+), 5 deletions(-) diff --git a/src/openpower/decoder/power_decoder2.py b/src/openpower/decoder/power_decoder2.py index 3517dafa..47114888 100644 --- a/src/openpower/decoder/power_decoder2.py +++ b/src/openpower/decoder/power_decoder2.py @@ -1503,7 +1503,7 @@ class PowerDecode2(PowerDecodeSubset): comb += ext_irq_ok.eq(ext_irq & msr[MSR.EE]) # v3.0B p944 (MSR.EE) comb += dec_irq_ok.eq(dec_spr[63] & msr[MSR.EE]) # 6.5.11 p1076 - comb += priv_ok.eq(is_priv_insn & msr[MSR.PR]) + #comb += priv_ok.eq(is_priv_insn & msr[MSR.PR]) comb += illeg_ok.eq(op.internal_op == MicrOp.OP_ILLEGAL) # absolute top priority: check for an instruction failed diff --git a/src/openpower/test/runner.py b/src/openpower/test/runner.py index 938fafe6..e205c7b0 100644 --- a/src/openpower/test/runner.py +++ b/src/openpower/test/runner.py @@ -15,7 +15,7 @@ related bugs: """ from nmigen import Module, ClockSignal -from copy import copy +from copy import copy, deepcopy from pprint import pprint # NOTE: to use cxxsim, export NMIGEN_SIM_MODE=cxxsim from the shell @@ -205,6 +205,13 @@ class TestRunnerBase(FHDLTestCase): ###### PREPARATION PHASE AT START OF TEST ####### + # HACK: if there is test memory and wb_get is in use, + # overwrite (reset) the wb_get memory dictionary with + # the test's memory contents + if self.rom is not None and test.mem is not None: + self.default_mem.clear() + self.default_mem.update(deepcopy(test.mem)) + for runner in state_list: yield from runner.prepare_for_test(test) @@ -491,11 +498,11 @@ class TestRunnerBase(FHDLTestCase): pprint (self.rom) dcache = hdlrun.issuer.core.fus.fus["mmu0"].alu.dcache icache = hdlrun.issuer.core.fus.fus["mmu0"].alu.icache - default_mem = self.rom + self.default_mem = deepcopy(self.rom) sim.add_sync_process(wrap(wb_get(dcache.bus, - default_mem, "DCACHE"))) + self.default_mem, "DCACHE"))) sim.add_sync_process(wrap(wb_get(icache.ibus, - default_mem, "ICACHE"))) + self.default_mem, "ICACHE"))) with sim.write_vcd("%s.vcd" % gtkname): sim.run() -- 2.30.2