From 76a53f2b56d0bef5b99eeeb592a8a5dd9e14d56f Mon Sep 17 00:00:00 2001 From: rwilbur Date: Thu, 16 Sep 2021 04:51:16 +0100 Subject: [PATCH] --- openpower/sv/svp64/appendix.mdwn | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/openpower/sv/svp64/appendix.mdwn b/openpower/sv/svp64/appendix.mdwn index 25bf3b641..d61703d56 100644 --- a/openpower/sv/svp64/appendix.mdwn +++ b/openpower/sv/svp64/appendix.mdwn @@ -163,7 +163,7 @@ followed by # Reduce mode Reduction in SVP64 is deterministic and somewhat of a misnomer. A normal -Vector ISA would have explicit Reduce opcodes with defibed characteristics +Vector ISA would have explicit Reduce opcodes with defined characteristics per operation: in SX Aurora there is even an additional scalar argument containing the initial reduction value. SVP64 fundamentally has to utilise *existing* Scalar Power ISA v3.0B operations, which presents some -- 2.30.2