From 76a67c0b877d94768df71bf232a5dda3d910511a Mon Sep 17 00:00:00 2001
From: lkcl <lkcl@web>
Date: Tue, 14 Sep 2021 16:29:01 +0100
Subject: [PATCH]

---
 openpower/sv/cr_ops.mdwn | 1 +
 1 file changed, 1 insertion(+)

diff --git a/openpower/sv/cr_ops.mdwn b/openpower/sv/cr_ops.mdwn
index 985c192cb..c04868f93 100644
--- a/openpower/sv/cr_ops.mdwn
+++ b/openpower/sv/cr_ops.mdwn
@@ -7,6 +7,7 @@ Links:
 * [[sv/branches]]
 * [[openpower/isa/sprset]]
 * [[openpower/isa/condition]]
+* [[openpower/isa/comparefixed]]
 
 Condition Register Fields are only 4 bits wide: this presents some
 interesting conceptual challenges for SVP64, particularly with respect to element
-- 
2.30.2