From 76bcb70b73f8b3594b9a901fe8ea4de6f2d1d426 Mon Sep 17 00:00:00 2001 From: Michael Nolan Date: Sat, 16 May 2020 11:30:52 -0400 Subject: [PATCH] Add ports to ilang for test_caller.py --- src/soc/alu/test/test_pipe_caller.py | 2 +- src/soc/branch/test/test_pipe_caller.py | 2 +- src/soc/cr/test/test_pipe_caller.py | 3 ++- src/soc/logical/test/test_pipe_caller.py | 2 +- src/soc/shift_rot/test/test_pipe_caller.py | 2 +- 5 files changed, 6 insertions(+), 5 deletions(-) diff --git a/src/soc/alu/test/test_pipe_caller.py b/src/soc/alu/test/test_pipe_caller.py index d56019b2..f42112e1 100644 --- a/src/soc/alu/test/test_pipe_caller.py +++ b/src/soc/alu/test/test_pipe_caller.py @@ -164,7 +164,7 @@ class ALUTestCase(FHDLTestCase): pspec = ALUPipeSpec(id_wid=2, op_wid=get_rec_width(rec)) alu = ALUBasePipe(pspec) - vl = rtlil.convert(alu, ports=[]) + vl = rtlil.convert(alu, ports=alu.ports()) with open("pipeline.il", "w") as f: f.write(vl) diff --git a/src/soc/branch/test/test_pipe_caller.py b/src/soc/branch/test/test_pipe_caller.py index 335b63ed..5f7a3fdd 100644 --- a/src/soc/branch/test/test_pipe_caller.py +++ b/src/soc/branch/test/test_pipe_caller.py @@ -103,7 +103,7 @@ class BranchTestCase(FHDLTestCase): pspec = ALUPipeSpec(id_wid=2, op_wid=get_rec_width(rec)) alu = BranchBasePipe(pspec) - vl = rtlil.convert(alu, ports=[]) + vl = rtlil.convert(alu, ports=alu.ports()) with open("logical_pipeline.il", "w") as f: f.write(vl) diff --git a/src/soc/cr/test/test_pipe_caller.py b/src/soc/cr/test/test_pipe_caller.py index 1ce5b520..10ede467 100644 --- a/src/soc/cr/test/test_pipe_caller.py +++ b/src/soc/cr/test/test_pipe_caller.py @@ -89,7 +89,8 @@ class CRTestCase(FHDLTestCase): pspec = ALUPipeSpec(id_wid=2, op_wid=get_rec_width(rec)) alu = CRBasePipe(pspec) - vl = rtlil.convert(alu, ports=[]) + ports = alu.ports() + vl = rtlil.convert(alu, ports=alu.ports()) with open("logical_pipeline.il", "w") as f: f.write(vl) diff --git a/src/soc/logical/test/test_pipe_caller.py b/src/soc/logical/test/test_pipe_caller.py index 190a9ade..79c1e291 100644 --- a/src/soc/logical/test/test_pipe_caller.py +++ b/src/soc/logical/test/test_pipe_caller.py @@ -166,7 +166,7 @@ class LogicalTestCase(FHDLTestCase): pspec = ALUPipeSpec(id_wid=2, op_wid=get_rec_width(rec)) alu = LogicalBasePipe(pspec) - vl = rtlil.convert(alu, ports=[]) + vl = rtlil.convert(alu, ports=alu.ports()) with open("logical_pipeline.il", "w") as f: f.write(vl) diff --git a/src/soc/shift_rot/test/test_pipe_caller.py b/src/soc/shift_rot/test/test_pipe_caller.py index 3244332b..dbd40923 100644 --- a/src/soc/shift_rot/test/test_pipe_caller.py +++ b/src/soc/shift_rot/test/test_pipe_caller.py @@ -183,7 +183,7 @@ class ALUTestCase(FHDLTestCase): pspec = ALUPipeSpec(id_wid=2, op_wid=get_rec_width(rec)) alu = ShiftRotBasePipe(pspec) - vl = rtlil.convert(alu, ports=[]) + vl = rtlil.convert(alu, ports=alu.ports()) with open("pipeline.il", "w") as f: f.write(vl) -- 2.30.2