From 76c4ee096bba99f787dd042bd9a6e988cf72f2dc Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Sun, 12 Feb 2017 17:42:57 +0100
Subject: [PATCH] Do not eagerly fix port widths on parameterized cells

---
 passes/hierarchy/hierarchy.cc | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc
index 4786aacaf..037fdb3b2 100644
--- a/passes/hierarchy/hierarchy.cc
+++ b/passes/hierarchy/hierarchy.cc
@@ -625,6 +625,9 @@ struct HierarchyPass : public Pass {
 			for (auto module : design->modules())
 			for (auto cell : module->cells())
 			{
+				if (GetSize(cell->parameters) != 0)
+					continue;
+
 				Module *m = design->module(cell->type);
 
 				if (m == nullptr)
-- 
2.30.2