From 76c677987c3a24bd67fb1449f898229b96422c63 Mon Sep 17 00:00:00 2001 From: lkcl Date: Thu, 21 Apr 2022 18:54:06 +0100 Subject: [PATCH] --- openpower/sv/biginteger/analysis.mdwn | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/openpower/sv/biginteger/analysis.mdwn b/openpower/sv/biginteger/analysis.mdwn index 85759aecd..f44212fff 100644 --- a/openpower/sv/biginteger/analysis.mdwn +++ b/openpower/sv/biginteger/analysis.mdwn @@ -115,7 +115,7 @@ microarchitecture, especially at the decode phase. Instead, Intel, in 2012, specifically added a `mulx` instruction, allowing both HI and LO halves of the multiply to reach registers. If done as a multiply-and-accumulate this becomes quite an expensive operation: -3 64-Bit in, 2 64-bit registers out). +(3 64-Bit in, 2 64-bit registers out). Long-multiplication may be performed a row at a time, starting with B0: -- 2.30.2