From 76d76a0e1cdcf2aa34d97e383c9ad148230ff9e5 Mon Sep 17 00:00:00 2001 From: Jim Wilson Date: Thu, 24 Sep 1992 22:39:45 -0700 Subject: [PATCH] (movdi... (movdi, movti, movdf, movtf): Make store zero to memory a separate case, only accept offsettable memory addresses, and call adj_offsettable_operand to calculate subword addresses. From-SVN: r2238 --- gcc/config/i960/i960.md | 48 ++++++++++++++++++++++++----------------- 1 file changed, 28 insertions(+), 20 deletions(-) diff --git a/gcc/config/i960/i960.md b/gcc/config/i960/i960.md index d1c241702ce..4ead2cd001e 100644 --- a/gcc/config/i960/i960.md +++ b/gcc/config/i960/i960.md @@ -773,8 +773,8 @@ ;; The store case can not be separate. See comment above. (define_insn "" - [(set (match_operand:DI 0 "general_operand" "=d,d,d,m") - (match_operand:DI 1 "general_operand" "dI,i,m,dJ"))] + [(set (match_operand:DI 0 "general_operand" "=d,d,d,m,o") + (match_operand:DI 1 "general_operand" "dI,i,m,d,J"))] "current_function_args_size == 0 && (register_operand (operands[0], DImode) || register_operand (operands[1], DImode) @@ -790,12 +790,13 @@ case 2: return \"ldl %1,%0\"; case 3: - if (operands[1] == const0_rtx) - return \"st g14,%0\;st g14,4(%0)\"; return \"stl %1,%0\"; + case 4: + operands[1] = adj_offsettable_operand (operands[0], 4); + return \"st g14,%0\;st g14,%1\"; } }" - [(set_attr "type" "move,load,load,store")]) + [(set_attr "type" "move,load,load,store,store")]) ;; The store case can not be separate. See comment above. (define_insn "" @@ -832,8 +833,8 @@ ;; The store case can not be separate. See comment above. (define_insn "" - [(set (match_operand:TI 0 "general_operand" "=d,d,d,m") - (match_operand:TI 1 "general_operand" "dI,i,m,dJ"))] + [(set (match_operand:TI 0 "general_operand" "=d,d,d,m,o") + (match_operand:TI 1 "general_operand" "dI,i,m,d,J"))] "current_function_args_size == 0 && (register_operand (operands[0], TImode) || register_operand (operands[1], TImode) @@ -849,12 +850,15 @@ case 2: return \"ldq %1,%0\"; case 3: - if (operands[1] == const0_rtx) - return \"st g14,%0\;st g14,4(%0)\;st g14,8(%0)\;st g14,12(%0)\"; return \"stq %1,%0\"; + case 4: + operands[1] = adj_offsettable_operand (operands[0], 4); + operands[2] = adj_offsettable_operand (operands[0], 8); + operands[3] = adj_offsettable_operand (operands[0], 12); + return \"st g14,%0\;st g14,%1\;st g14,%2\;st g14,%3\"; } }" - [(set_attr "type" "move,load,load,store")]) + [(set_attr "type" "move,load,load,store,store")]) ;; The store case can not be separate. See comment above. (define_insn "" @@ -945,8 +949,8 @@ }") (define_insn "" - [(set (match_operand:DF 0 "general_operand" "=r,f,d,d,m") - (match_operand:DF 1 "fpmove_src_operand" "r,GH,F,m,dG"))] + [(set (match_operand:DF 0 "general_operand" "=r,f,d,d,m,o") + (match_operand:DF 1 "fpmove_src_operand" "r,GH,F,m,d,G"))] "current_function_args_size == 0 && (register_operand (operands[0], DFmode) || register_operand (operands[1], DFmode) @@ -967,12 +971,13 @@ case 3: return \"ldl %1,%0\"; case 4: - if (operands[1] == CONST0_RTX (DFmode)) - return \"st g14,%0\;st g14,4(%0)\"; return \"stl %1,%0\"; + case 5: + operands[1] = adj_offsettable_operand (operands[0], 4); + return \"st g14,%0\;st g14,%1\"; } }" - [(set_attr "type" "move,move,load,fpload,fpstore")]) + [(set_attr "type" "move,move,load,fpload,fpstore,fpstore")]) (define_insn "" [(set (match_operand:DF 0 "general_operand" "=r,f,d,d,m") @@ -1856,8 +1861,8 @@ }") (define_insn "" - [(set (match_operand:TF 0 "general_operand" "=r,f,d,d,m") - (match_operand:TF 1 "fpmove_src_operand" "r,GH,F,m,dG"))] + [(set (match_operand:TF 0 "general_operand" "=r,f,d,d,m,o") + (match_operand:TF 1 "fpmove_src_operand" "r,GH,F,m,d,G"))] "current_function_args_size == 0 && (register_operand (operands[0], TFmode) || register_operand (operands[1], TFmode) @@ -1878,12 +1883,15 @@ case 3: return \"ldq %1,%0\"; case 4: - if (operands[1] == CONST0_RTX (TFmode)) - return \"st g14,%0\;st g14,4(%0)\;st g14,8(%0)\;st g14,12(%0)\"; return \"stq %1,%0\"; + case 5: + operands[1] = adj_offsettable_operand (operands[0], 4); + operands[2] = adj_offsettable_operand (operands[0], 8); + operands[3] = adj_offsettable_operand (operands[0], 12); + return \"st g14,%0\;st g14,%1\;st g14,%2\;st g14,%3\"; } }" - [(set_attr "type" "move,move,load,fpload,fpstore")]) + [(set_attr "type" "move,move,load,fpload,fpstore,fpstore")]) (define_insn "" [(set (match_operand:TF 0 "general_operand" "=r,f,d,d,m") -- 2.30.2