From 76d9664f4c93264744b006cb8243319c480aae5b Mon Sep 17 00:00:00 2001
From: lkcl <lkcl@web>
Date: Thu, 21 Apr 2022 14:06:48 +0100
Subject: [PATCH]

---
 openpower/sv/biginteger/analysis.mdwn | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/openpower/sv/biginteger/analysis.mdwn b/openpower/sv/biginteger/analysis.mdwn
index 408a27bc8..cdcddc61e 100644
--- a/openpower/sv/biginteger/analysis.mdwn
+++ b/openpower/sv/biginteger/analysis.mdwn
@@ -135,7 +135,8 @@ of Knuth M: <https://git.libre-soc.org/?p=libreriscv.git;a=blob;f=openpower/sv/b
 
 ```
       // this becomes the basis for sv.madded in RS=RC Mode,
-      // where k is RC
+      // where k is RC. k takes the upper half of product
+      // and adds it in on the next iteration
       k = 0;
       for (i = 0; i < m; i++) {
          unsigned product = u[i]*v[j] + k;
@@ -168,7 +169,7 @@ RA*RB+RC+RD cannot overflow, so does not require
 setting an additional CA flag. We first cover the chain of
 RA*RB+RC as follows:
 
-    RT0, RC0 = RA0 * RB0 + RC
+    RT0, RC0 = RA0 * RB0 + 0
           |
           +----------------+
                            |
-- 
2.30.2