From 76ee8711f8e04b9ada61e91e6ac6f1fd01a4ca1e Mon Sep 17 00:00:00 2001
From: Andrew Waterman <waterman@s141.Millennium.Berkeley.EDU>
Date: Tue, 25 Jan 2011 22:56:38 -0800
Subject: [PATCH] [sim,opcodes] add mulhsu instruction

---
 riscv/execute.h      | 7 ++++++-
 riscv/insns/mulhsu.h | 8 ++++++++
 2 files changed, 14 insertions(+), 1 deletion(-)
 create mode 100644 riscv/insns/mulhsu.h

diff --git a/riscv/execute.h b/riscv/execute.h
index 8539974..844745d 100644
--- a/riscv/execute.h
+++ b/riscv/execute.h
@@ -334,13 +334,18 @@ switch((insn.bits >> 0x0) & 0x7f)
           #include "insns/sll.h"
           break;
         }
+        if((insn.bits & 0x1ffff) == 0x4b3)
+        {
+          #include "insns/mulh.h"
+          break;
+        }
         #include "insns/unimp.h"
       }
       case 0x2:
       {
         if((insn.bits & 0x1ffff) == 0x533)
         {
-          #include "insns/mulh.h"
+          #include "insns/mulhsu.h"
           break;
         }
         if((insn.bits & 0x1ffff) == 0x133)
diff --git a/riscv/insns/mulhsu.h b/riscv/insns/mulhsu.h
new file mode 100644
index 0000000..506424d
--- /dev/null
+++ b/riscv/insns/mulhsu.h
@@ -0,0 +1,8 @@
+if(xpr64)
+{
+  int64_t a = RS1;
+  uint64_t b = RS2;
+  RD = (int128_t(a) * uint128_t(b)) >> 64;
+}
+else
+  RD = sext32((sreg_t(RS1) * reg_t(RS2)) >> 32);
-- 
2.30.2