From 772c69e99d2e68af2adb0cc74ad4eb365b10a210 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Tue, 16 Jul 2019 17:41:07 +0100 Subject: [PATCH] whoops fpnorm out by one bit in new FPMSBHigh class --- src/ieee754/fcvt/test/up_fcvt_data_16_32.py | 1 + src/ieee754/fpcommon/postnormalise.py | 3 +-- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/ieee754/fcvt/test/up_fcvt_data_16_32.py b/src/ieee754/fcvt/test/up_fcvt_data_16_32.py index 24abc340..2dbcb7fb 100644 --- a/src/ieee754/fcvt/test/up_fcvt_data_16_32.py +++ b/src/ieee754/fcvt/test/up_fcvt_data_16_32.py @@ -1,3 +1,4 @@ def regressions(): + yield 0x110, yield 0x7e83, yield 0xaf47, diff --git a/src/ieee754/fpcommon/postnormalise.py b/src/ieee754/fpcommon/postnormalise.py index 5bfb447c..196d158a 100644 --- a/src/ieee754/fpcommon/postnormalise.py +++ b/src/ieee754/fpcommon/postnormalise.py @@ -80,7 +80,7 @@ class FPNorm1ModSingle(Elaboratable): msr = MultiShiftRMerge(mwid+2, espec) m.submodules.multishift_r = msr - msb = FPMSBHigh(mwid, espec[0], True) + msb = FPMSBHigh(mwid+1, espec[0], True) m.submodules.norm_msb = msb m.d.comb += i.eq(self.i) @@ -97,7 +97,6 @@ class FPNorm1ModSingle(Elaboratable): with m.If(decrease): # make sure that the amount to decrease by does NOT # go below the minimum non-INF/NaN exponent - temp_m = Signal(mwid+1, reset_less=True) m.d.comb += msb.limclz.eq(insel_z.exp_sub_n126) m.d.comb += [ # cat round and guard bits back into the mantissa -- 2.30.2