From 774cccdc1a36493ae6925148c08dfbdcb2789e0c Mon Sep 17 00:00:00 2001 From: Jakub Jelinek Date: Tue, 25 Jul 2017 15:35:17 +0200 Subject: [PATCH] re PR target/81532 (insn does not satisfy its constraints: extract_constrain_insn, at recog.c:2213) PR target/81532 * config/i386/constraints.md (Yd, Ye): Use ALL_SSE_REGS for TARGET_AVX512DQ rather than TARGET_AVX512BW. * gcc.target/i386/pr80833-3.c: New test. * gcc.target/i386/avx512dq-pr81532.c: New test. * gcc.target/i386/avx512bw-pr81532.c: New test. From-SVN: r250520 --- gcc/ChangeLog | 30 +++++++++++-------- gcc/config/i386/constraints.md | 8 ++--- gcc/testsuite/ChangeLog | 29 +++++++++++------- .../gcc.target/i386/avx512bw-pr81532.c | 5 ++++ .../gcc.target/i386/avx512dq-pr81532.c | 12 ++++++++ gcc/testsuite/gcc.target/i386/pr80833-3.c | 14 +++++++++ 6 files changed, 71 insertions(+), 27 deletions(-) create mode 100644 gcc/testsuite/gcc.target/i386/avx512bw-pr81532.c create mode 100644 gcc/testsuite/gcc.target/i386/avx512dq-pr81532.c create mode 100644 gcc/testsuite/gcc.target/i386/pr80833-3.c diff --git a/gcc/ChangeLog b/gcc/ChangeLog index c55e67a72e8..047f9218e0f 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2017-07-25 Jakub Jelinek + + PR target/81532 + * config/i386/constraints.md (Yd, Ye): Use ALL_SSE_REGS for + TARGET_AVX512DQ rather than TARGET_AVX512BW. + 2017-07-25 Tamar Christina * config/arm/parsecpu.awk (all_cores): Remove duplicates. @@ -799,7 +805,7 @@ 2017-07-17 Sebastian Huber - * gcc/config/sparc/rtemself.h (TARGET_OS_CPP_BUILTINS): Add + * config/sparc/rtemself.h (TARGET_OS_CPP_BUILTINS): Add conditional builtin define __FIX_LEON3FT_B2BST. 2017-07-17 Daniel Cederman @@ -1903,7 +1909,7 @@ 2017-07-06 Julia Koval - * gcc/config/i386/i386.c (ix86_erase_embedded_rounding): + * config/i386/i386.c (ix86_erase_embedded_rounding): Remove code for old rounding pattern. 2017-07-06 Richard Earnshaw @@ -15356,7 +15362,7 @@ 2017-02-06 Palmer Dabbelt * config/riscv/riscv.c: New file. - * gcc/common/config/riscv/riscv-common.c: Likewise. + * common/config/riscv/riscv-common.c: Likewise. * config.gcc: Likewise. * config/riscv/constraints.md: Likewise. * config/riscv/elf.h: Likewise. @@ -16619,7 +16625,7 @@ * config/i386/avx512bwintrin.h: Add k-mask test, kortest intrinsics. * config/i386/avx512dqintrin.h: Ditto. * config/i386/avx512fintrin.h: Ditto. - * gcc/config/i386/i386.c: Handle new builtins. + * config/i386/i386.c: Handle new builtins. * config/i386/i386-builtin.def: Add new builtins. * config/i386/sse.md (ktest, kortest): New. (UNSPEC_KORTEST, UNSPEC_KTEST): New. @@ -16800,7 +16806,7 @@ * config/i386/avx512dqintrin.h: Ditto. * config/i386/avx512fintrin.h: Ditto. * config/i386/i386-builtin-types.def: Add new types. - * gcc/config/i386/i386.c: Handle new types. + * config/i386/i386.c: Handle new types. * config/i386/i386-builtin.def (__builtin_ia32_kshiftliqi) (__builtin_ia32_kshiftlihi, __builtin_ia32_kshiftlisi) (__builtin_ia32_kshiftlidi, __builtin_ia32_kshiftriqi) @@ -16823,14 +16829,14 @@ (with_madd4): Add validation. (all_defaults): Add madd4. * config/mips/mips.opt (mmadd4): New option. - * gcc/config/mips/mips.h (OPTION_DEFAULT_SPECS): Add a default for + * config/mips/mips.h (OPTION_DEFAULT_SPECS): Add a default for mmadd4. (TARGET_CPU_CPP_BUILTINS): Add builtin_define for __mips_no_madd4. (ISA_HAS_UNFUSED_MADD4): Gate with mips_madd4. (ISA_HAS_FUSED_MADD4): Likewise. - * gcc/doc/invoke.texi (-mmadd4): Document the new option. - * gcc/doc/install.texi (--with-madd4): Document the new option. + * doc/invoke.texi (-mmadd4): Document the new option. + * doc/install.texi (--with-madd4): Document the new option. 2017-01-19 Jiong Wang @@ -16968,12 +16974,12 @@ (with_lxc1_sxc1): Add validation. (all_defaults): Add lxc1-sxc1. * config/mips/mips.opt (mlxc1-sxc1): New option. - * gcc/config/mips/mips.h (OPTION_DEFAULT_SPECS): Add a default for + * config/mips/mips.h (OPTION_DEFAULT_SPECS): Add a default for mlxc1-sxc1. (TARGET_CPU_CPP_BUILTINS): Add builtin_define for __mips_no_lxc1_sxc1. (ISA_HAS_LXC1_SXC1): Gate with mips_lxc1_sxc1. - * gcc/doc/invoke.texi (-mlxc1-sxc1): Document the new option. + * doc/invoke.texi (-mlxc1-sxc1): Document the new option. * doc/install.texi (--with-lxc1-sxc1): Document the new option. 2017-01-19 Richard Biener @@ -18390,8 +18396,8 @@ 'arm_const_bounds'. * config/arm/types.md (coproc): New. * config/arm/unspecs.md (VUNSPEC_CDP, VUNSPEC_CDP2): New. - * gcc/doc/extend.texi (ACLE): Add a mention of Coprocessor intrinsics. - * gcc/doc/sourcebuild.texi (arm_coproc1_ok, arm_coproc2_ok, + * doc/extend.texi (ACLE): Add a mention of Coprocessor intrinsics. + * doc/sourcebuild.texi (arm_coproc1_ok, arm_coproc2_ok, arm_coproc3_ok, arm_coproc4_ok): Document new effective targets. 2017-01-06 Andre Vieira diff --git a/gcc/config/i386/constraints.md b/gcc/config/i386/constraints.md index f94e274358b..98c05c9ebab 100644 --- a/gcc/config/i386/constraints.md +++ b/gcc/config/i386/constraints.md @@ -138,19 +138,19 @@ (define_register_constraint "Yd" "TARGET_INTER_UNIT_MOVES_TO_VEC - ? (TARGET_AVX512BW + ? (TARGET_AVX512DQ ? ALL_SSE_REGS : (TARGET_SSE4_1 ? SSE_REGS : NO_REGS)) : NO_REGS" - "@internal Any EVEX encodable SSE register (@code{%xmm0-%xmm31}) for AVX512BW target or any SSE register for SSE4_1 target, when inter-unit moves to vector registers are enabled.") + "@internal Any EVEX encodable SSE register (@code{%xmm0-%xmm31}) for AVX512DQ target or any SSE register for SSE4_1 target, when inter-unit moves to vector registers are enabled.") (define_register_constraint "Ye" "TARGET_INTER_UNIT_MOVES_FROM_VEC - ? (TARGET_AVX512BW + ? (TARGET_AVX512DQ ? ALL_SSE_REGS : (TARGET_SSE4_1 ? SSE_REGS : NO_REGS)) : NO_REGS" - "@internal Any EVEX encodable SSE register (@code{%xmm0-%xmm31}) for AVX512BW target or any SSE register for SSE4_1 target, when inter-unit moves from vector registers are enabled.") + "@internal Any EVEX encodable SSE register (@code{%xmm0-%xmm31}) for AVX512DQ target or any SSE register for SSE4_1 target, when inter-unit moves from vector registers are enabled.") (define_register_constraint "Ym" "TARGET_MMX && TARGET_INTER_UNIT_MOVES_TO_VEC ? MMX_REGS : NO_REGS" diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 0aee7d90946..90a73a13529 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,10 @@ +2017-07-25 Jakub Jelinek + + PR target/81532 + * gcc.target/i386/pr80833-3.c: New test. + * gcc.target/i386/avx512dq-pr81532.c: New test. + * gcc.target/i386/avx512bw-pr81532.c: New test. + 2017-07-25 Richard Biener PR tree-optimization/81455 @@ -10,7 +17,7 @@ 2017-07-25 Wilco Dijkstra - * testsuite/gcc.target/aarch64/pr79041-2.c: Improve test. + * gcc.target/aarch64/pr79041-2.c: Improve test. 2017-07-25 Richard Biener @@ -545,7 +552,7 @@ 2017-07-11 Michael Collison - * testsuite/gcc.target/aarch64/cmp-2.c: New testcase. + * gcc.target/aarch64/cmp-2.c: New testcase. 2017-07-11 Paolo Carlini @@ -1721,7 +1728,7 @@ * gcc.dg/fold-bcopy.c: New test. * gcc.dg/tree-ssa/ssa-dse-30.c: Likewise.. * gcc.dg/tree-ssa/alias-36.c: Likewise. - * gcc/testsuite/gcc.dg/pr79214.c: Adjust. + * gcc.dg/pr79214.c: Adjust. * gcc.dg/tree-prof/val-prof-7.c: Likewise. * gcc.dg/Wsizeof-pointer-memaccess1.c: Likewise. * gcc.dg/builtins-nonnull.c: Likewise. @@ -2062,12 +2069,12 @@ 2017-06-08 Will Schmidt - * testsuite/gcc.target/powerpc/fold-vec-logical-eqv-char.c: New. - * testsuite/gcc.target/powerpc/fold-vec-logical-eqv-float.c: New. - * testsuite/gcc.target/powerpc/fold-vec-logical-eqv-floatdouble.c: New. - * testsuite/gcc.target/powerpc/fold-vec-logical-eqv-int.c: New. - * testsuite/gcc.target/powerpc/fold-vec-logical-eqv-longlong.c: New. - * testsuite/gcc.target/powerpc/fold-vec-logical-eqv-short.c: New. + * gcc.target/powerpc/fold-vec-logical-eqv-char.c: New. + * gcc.target/powerpc/fold-vec-logical-eqv-float.c: New. + * gcc.target/powerpc/fold-vec-logical-eqv-floatdouble.c: New. + * gcc.target/powerpc/fold-vec-logical-eqv-int.c: New. + * gcc.target/powerpc/fold-vec-logical-eqv-longlong.c: New. + * gcc.target/powerpc/fold-vec-logical-eqv-short.c: New. 2017-06-08 Jakub Jelinek @@ -3790,8 +3797,8 @@ 2017-05-08 Wilco Dijkstra - * testsuite/gcc.dg/vect/vect-44.c: Add -fno-vect-cost-model. - * gcc/testsuite/gcc.dg/vect/vect-50.c: Likewise. + * gcc.dg/vect/vect-44.c: Add -fno-vect-cost-model. + * gcc.dg/vect/vect-50.c: Likewise. 2017-05-07 Jeff Law diff --git a/gcc/testsuite/gcc.target/i386/avx512bw-pr81532.c b/gcc/testsuite/gcc.target/i386/avx512bw-pr81532.c new file mode 100644 index 00000000000..6ebaed6f715 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512bw-pr81532.c @@ -0,0 +1,5 @@ +/* PR target/81532 */ +/* { dg-do compile { target int128 } } */ +/* { dg-options "-O2 -mavx512bw -mavx512vl -mno-avx512dq" } */ + +#include "avx512dq-pr81532.c" diff --git a/gcc/testsuite/gcc.target/i386/avx512dq-pr81532.c b/gcc/testsuite/gcc.target/i386/avx512dq-pr81532.c new file mode 100644 index 00000000000..39632a2c482 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512dq-pr81532.c @@ -0,0 +1,12 @@ +/* PR target/81532 */ +/* { dg-do compile { target int128 } } */ +/* { dg-options "-O2 -mavx512dq -mavx512vl -mno-avx512bw" } */ + +typedef unsigned __int128 V __attribute__ ((vector_size (64))); + +V +foo (V c) +{ + c >>= 0 != c; + return c; +} diff --git a/gcc/testsuite/gcc.target/i386/pr80833-3.c b/gcc/testsuite/gcc.target/i386/pr80833-3.c new file mode 100644 index 00000000000..6d5b8bb6b69 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr80833-3.c @@ -0,0 +1,14 @@ +/* { dg-do compile { target int128 } } */ +/* { dg-options "-O2 -mavx512dq -mavx512vl -mno-avx512bw -mtune=intel" } */ + +__int128 test (__int128 a) +{ + asm ("" : "+v" (a) : : "xmm0", "xmm1", "xmm2", "xmm3", + "xmm4", "xmm5", "xmm6", "xmm7", + "xmm8", "xmm9", "xmm10", "xmm11", + "xmm12", "xmm13", "xmm14", "xmm15"); + return a; +} + +/* { dg-final { scan-assembler "pinsrq" } } */ +/* { dg-final { scan-assembler "pextrq" } } */ -- 2.30.2