From 77658122c2d692413edf7baa1490fb31bd113078 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Thu, 28 May 2020 13:21:28 +0100 Subject: [PATCH] debug-print rd/wr rel in test_alu_compunit --- src/soc/fu/compunits/test/test_alu_compunit.py | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/src/soc/fu/compunits/test/test_alu_compunit.py b/src/soc/fu/compunits/test/test_alu_compunit.py index c14d683f..3b2dc1ec 100644 --- a/src/soc/fu/compunits/test/test_alu_compunit.py +++ b/src/soc/fu/compunits/test/test_alu_compunit.py @@ -111,7 +111,11 @@ class TestRunner(FHDLTestCase): sim = Simulator(m) sim.add_clock(1e-6) + def process(): + yield cu.issue_i.eq(0) + yield + for test in self.test_data: print(test.name) program = test.program @@ -134,9 +138,17 @@ class TestRunner(FHDLTestCase): fn_unit = yield pdecode2.e.fn_unit self.assertEqual(fn_unit, Function.ALU.value) yield from set_operand(cu, pdecode2, sim) + rd_rel_o = yield cu.rd.rel + wr_rel_o = yield cu.wr.rel + print ("before inputs, rd_rel, wr_rel: ", + bin(rd_rel_o), bin(wr_rel_o)) yield from set_cu_inputs(cu, pdecode2, sim) yield from set_extra_cu_inputs(cu, pdecode2, sim) yield + rd_rel_o = yield cu.rd.rel + wr_rel_o = yield cu.wr.rel + print ("after inputs, rd_rel, wr_rel: ", + bin(rd_rel_o), bin(wr_rel_o)) opname = code.split(' ')[0] yield from sim.call(opname) index = sim.pc.CIA.value//4 -- 2.30.2