From 7771c7d9180d369299fc754e640733e309d9adf6 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sun, 18 Apr 2021 21:39:25 +0100 Subject: [PATCH] sort out names --- libresoc/core.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/libresoc/core.py b/libresoc/core.py index 2035df2..5e6c02a 100644 --- a/libresoc/core.py +++ b/libresoc/core.py @@ -275,7 +275,7 @@ class LibreSoC(CPU): self.pll_ana_o = Signal() self.cpu_params['i_clk_sel_i'] = self.clk_sel self.cpu_params['o_pll_18_o'] = self.pll_18_o - self.cpu_params['o_vco_test_ana_o'] = self.pll_ana_o + self.cpu_params['o_vco_test_ana'] = self.pll_ana_o # add wishbone buses to cpu params self.cpu_params.update(make_wb_bus("ibus", ibus, True)) -- 2.30.2