From 778be293befd8146d0a308a32137ebc9248d480a Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Tue, 23 Jul 2019 17:27:22 +0100 Subject: [PATCH] hack which happens to get fsqrt preliminarily working --- src/ieee754/fpdiv/div0.py | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/ieee754/fpdiv/div0.py b/src/ieee754/fpdiv/div0.py index 16a78c6e..32d0d17c 100644 --- a/src/ieee754/fpdiv/div0.py +++ b/src/ieee754/fpdiv/div0.py @@ -103,11 +103,11 @@ class FPDivStage0Mod(Elaboratable): with m.Elif(self.i.ctx.op == 1): am0 = Signal(len(self.i.a.m)+3, reset_less=True) with m.If(self.i.a.e[0]): - m.d.comb += am0.eq(Cat(0,0, self.i.a.m, 0)) - m.d.comb += self.o.z.e.eq(((self.i.a.e+1) >> 1)) + m.d.comb += am0.eq(Cat(self.i.a.m, 0)<<(extra-2)) + m.d.comb += self.o.z.e.eq(((self.i.a.e+1) >> 1)+1) with m.Else(): - m.d.comb += am0.eq(Cat(0, 0, 0, self.i.a.m)) - m.d.comb += self.o.z.e.eq((self.i.a.e >> 1)) + m.d.comb += am0.eq(Cat(0, self.i.a.m)<<(extra-2)) + m.d.comb += self.o.z.e.eq((self.i.a.e >> 1)+1) m.d.comb += [self.o.z.s.eq(self.i.a.s), self.o.divisor_radicand.eq(am0), -- 2.30.2