From 7790105913cf53cd8a2d01968c19e4bb7f003585 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Wed, 24 Sep 2014 12:13:43 +0200 Subject: [PATCH] realign rxdata / rxcharisk directly in gtx --- lib/sata/k7sataphy/gtx.py | 29 +++++++++++++++++++++++++---- 1 file changed, 25 insertions(+), 4 deletions(-) diff --git a/lib/sata/k7sataphy/gtx.py b/lib/sata/k7sataphy/gtx.py index 89d0aa41..a4ebbb48 100644 --- a/lib/sata/k7sataphy/gtx.py +++ b/lib/sata/k7sataphy/gtx.py @@ -27,7 +27,6 @@ class GTXE2_CHANNEL(Module): self.rxuserrdy = Signal() # Receive Ports - 8b10b Decoder - self.rxchariscomma = Signal(2) self.rxcharisk = Signal(2) self.rxdisperr = Signal(2) self.rxnotintable = Signal(2) @@ -124,6 +123,9 @@ class GTXE2_CHANNEL(Module): } rxcdr_cfg = cdr_config[start_speed] + rxdata = Signal(16) + rxcharisk = Signal(2) + self.specials += \ Instance("GTXE2_CHANNEL", # Simulation-Only Attributes @@ -492,7 +494,7 @@ class GTXE2_CHANNEL(Module): i_RXUSRCLK2=self.rxusrclk2, # Receive Ports - FPGA RX interface Ports - i_RXDATA=self.rxdata, + i_RXDATA=rxdata, # Receive Ports - Pattern Checker Ports #o_RXPRBSERR=, @@ -629,8 +631,8 @@ class GTXE2_CHANNEL(Module): i_RXSLIDE=0, # Receive Ports - RX8B/10B Decoder Ports - o_RXCHARISCOMMA=self.rxchariscomma, - o_RXCHARISK=self.rxcharisk, + #o_RXCHARISCOMMA=, + o_RXCHARISK=rxcharisk, # Receive Ports - Rx Channel Bonding Ports i_RXCHBONDI=0, @@ -759,3 +761,22 @@ class GTXE2_CHANNEL(Module): #o_TXQPISENN=, #o_TXQPISENP= ) + + # realign rxdata / rxcharisk + rxdata_r = Signal(dw) + rxcharisk_r = Signal(dw//8) + self.sync.sata_rx += [ + rxdata_r.eq(rxdata), + rxcharisk_r.eq(rxcharisk) + ] + cases = {} + cases[1<<0] = [ + self.rxdata.eq(rx_data_r[0:dw]), + self.rxcharisk.eq(rx_charisk_r[0:dw//8]) + ] + for i in range(1, dw//8): + cases[1<