From 7792d774e0ab4f3d45d758da1e9ac80fef0d7934 Mon Sep 17 00:00:00 2001 From: Bas Nieuwenhuizen Date: Sat, 18 Jan 2020 23:32:46 +0100 Subject: [PATCH] radv: Optimize emitting index buffer changes. Since the direct indexed draw packet has the address/count info inline, there is no sense in emitting the base and size. No real significant changes found during benchmarks. Reviewed-by: Samuel Pitoiset Tested-by: Marge Bot Part-of: --- src/amd/vulkan/radv_cmd_buffer.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index 549b7e8843d..12d5d60d91a 100644 --- a/src/amd/vulkan/radv_cmd_buffer.c +++ b/src/amd/vulkan/radv_cmd_buffer.c @@ -2063,7 +2063,7 @@ radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer) } static void -radv_emit_index_buffer(struct radv_cmd_buffer *cmd_buffer) +radv_emit_index_buffer(struct radv_cmd_buffer *cmd_buffer, bool indirect) { struct radeon_cmdbuf *cs = cmd_buffer->cs; struct radv_cmd_state *state = &cmd_buffer->state; @@ -2081,6 +2081,11 @@ radv_emit_index_buffer(struct radv_cmd_buffer *cmd_buffer) state->last_index_type = state->index_type; } + /* For the direct indexed draws we use DRAW_INDEX_2, which includes + * the index_va and max_index_count already. */ + if (!indirect) + return; + radeon_emit(cs, PKT3(PKT3_INDEX_BASE, 1, 0)); radeon_emit(cs, state->index_va); radeon_emit(cs, state->index_va >> 32); @@ -4665,7 +4670,7 @@ radv_emit_all_graphics_states(struct radv_cmd_buffer *cmd_buffer, if (info->indexed) { if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_INDEX_BUFFER) - radv_emit_index_buffer(cmd_buffer); + radv_emit_index_buffer(cmd_buffer, info->indirect); } else { /* On GFX7 and later, non-indexed draws overwrite VGT_INDEX_TYPE, * so the state must be re-emitted before the next indexed -- 2.30.2