From 779f8dd7a3d915a57f92aef71aab535a7182631b Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Wed, 16 Feb 2022 14:16:18 +0000 Subject: [PATCH] drop clock frequency to 25 mhz and disable abc9 (it fails to build) --- src/ls2.py | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/src/ls2.py b/src/ls2.py index cd3b4c8..78e4399 100644 --- a/src/ls2.py +++ b/src/ls2.py @@ -271,11 +271,12 @@ if __name__ == "__main__": fw_addr=fw_addr, ddr_pins=ddr_pins, uart_pins=uart_pins, - firmware=firmware) + firmware=firmware, + clk_freq=25e6) - if toolchain == 'Trellis': + #if toolchain == 'Trellis': # add -abc9 option to yosys synth_ecp5 - os.environ['NMIGEN_synth_opts'] = '-abc9' + # os.environ['NMIGEN_synth_opts'] = '-abc9' if platform is not None: # build and upload it -- 2.30.2