From 77a05b78e81af7fb2ca992ae8b6b5bd550310ec8 Mon Sep 17 00:00:00 2001 From: Mateusz Holenko Date: Tue, 14 Apr 2020 21:43:58 +0200 Subject: [PATCH] soc_core: Fix region type generation Include information about being a linker region. --- litex/soc/integration/soc_core.py | 2 ++ 1 file changed, 2 insertions(+) diff --git a/litex/soc/integration/soc_core.py b/litex/soc/integration/soc_core.py index b1209a00..3eb0016c 100644 --- a/litex/soc/integration/soc_core.py +++ b/litex/soc/integration/soc_core.py @@ -244,6 +244,8 @@ class SoCCore(LiteXSoC): for region in self.bus.regions.values(): region.length = region.size region.type = "cached" if region.cached else "io" + if region.linker: + region.type += "+linker" self.csr_regions = self.csr.regions for name, value in self.config.items(): self.add_config(name, value) -- 2.30.2