From 77a5bc0d04f9e8a2dc584e4439c4af61c947b464 Mon Sep 17 00:00:00 2001 From: Giacomo Travaglini Date: Fri, 8 Nov 2019 15:53:11 +0000 Subject: [PATCH] tests: Remove Noncoherent cache from regressions Change-Id: I1d499477acec09fd0b36e3b7c2f5eecee737bd93 Signed-off-by: Giacomo Travaglini Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22683 Reviewed-by: Jason Lowe-Power Reviewed-by: Bobby R. Bruce Maintainer: Jason Lowe-Power Tested-by: kokoro --- tests/configs/base_config.py | 13 +------------ 1 file changed, 1 insertion(+), 12 deletions(-) diff --git a/tests/configs/base_config.py b/tests/configs/base_config.py index d79496d7c..bf0b00df8 100644 --- a/tests/configs/base_config.py +++ b/tests/configs/base_config.py @@ -278,19 +278,8 @@ class BaseFSSystem(BaseSystem): # the physmem name to avoid bumping all the reference stats system.physmem = [self.mem_class(range = r) for r in system.mem_ranges] - system.llc = [NoncoherentCache(addr_ranges = [r], - size = '4kB', - assoc = 2, - mshrs = 128, - tag_latency = 10, - data_latency = 10, - sequential_access = True, - response_latency = 20, - tgts_per_mshr = 8) - for r in system.mem_ranges] for i in range(len(system.physmem)): - system.physmem[i].port = system.llc[i].mem_side - system.llc[i].cpu_side = system.membus.master + system.physmem[i].port = system.membus.master # create the iocache, which by default runs at the system clock system.iocache = IOCache(addr_ranges=system.mem_ranges) -- 2.30.2