From 77b0afd6ecb76d9905aef53e26fa8dc1c477f8ee Mon Sep 17 00:00:00 2001 From: lkcl Date: Thu, 13 Oct 2022 01:28:52 +0100 Subject: [PATCH] --- openpower/sv/svp64.mdwn | 4 ---- 1 file changed, 4 deletions(-) diff --git a/openpower/sv/svp64.mdwn b/openpower/sv/svp64.mdwn index a7d23f106..c1bb830c7 100644 --- a/openpower/sv/svp64.mdwn +++ b/openpower/sv/svp64.mdwn @@ -209,8 +209,6 @@ on context after decoding of the Scalar suffix: | Field Name | Field bits | Description | |------------|------------|----------------------------------------| | ELWIDTH | `4:5` | Element Width | -| PACK | `4` | Pack subvectors (sv.setvl only) | -| UNPACK | `5` | Unpack subvectors (sv.setvl only | | ELWIDTH_SRC | `6:7` | Element Width for Source | | EXTRA | `10:18` | Register Extra encoding | | MODE | `19:23` | changes Vector behaviour | @@ -218,8 +216,6 @@ on context after decoding of the Scalar suffix: * MODE changes the behaviour of the SV operation (result saturation, mapreduce) * SUBVL groups elements together into vec2, vec3, vec4 for use in 3D and Audio/Video DSP work * ELWIDTH and ELWIDTH_SRC overrides the instruction's destination and source operand width -* PACK and UNPACK apply to Subvector structure packing: may only be - set by the `sv.setvl` instruction. * MASK (and MASK_SRC) and MASKMODE provide predication (two types of sources: scalar INT and Vector CR). * Bits 10 to 18 (EXTRA) are further decoded depending on the RM category for the instruction, which is determined only by decoding the Scalar 32 bit suffix. -- 2.30.2