From 77b6f50ce382b37801c63f8a0d06c02bedbfcafa Mon Sep 17 00:00:00 2001 From: =?utf8?q?Adri=C3=A0=20Armejach?= Date: Wed, 18 Dec 2019 15:40:17 +0100 Subject: [PATCH] arch-arm: Fix decoding of LDFF1x scalar plus scalar First-faulting loads do allow Rm == 0x1f. Change-Id: Ib9bcb55e126653813fdbb7c29970af23a2471ebb Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23803 Reviewed-by: Giacomo Travaglini Maintainer: Giacomo Travaglini Tested-by: kokoro --- src/arch/arm/isa/formats/sve_2nd_level.isa | 4 ---- 1 file changed, 4 deletions(-) diff --git a/src/arch/arm/isa/formats/sve_2nd_level.isa b/src/arch/arm/isa/formats/sve_2nd_level.isa index c06d7f6a7..8bde189b2 100644 --- a/src/arch/arm/isa/formats/sve_2nd_level.isa +++ b/src/arch/arm/isa/formats/sve_2nd_level.isa @@ -3132,10 +3132,6 @@ namespace Aarch64 IntRegIndex rm = (IntRegIndex) (uint8_t) bits(machInst, 20, 16); IntRegIndex pg = (IntRegIndex) (uint8_t) bits(machInst, 12, 10); - if (rm == 0x1f) { - return new Unknown64(machInst); - } - return decodeSveContigLoadSSInsts( bits(machInst, 24, 21), machInst, zt, pg, rn, rm, true); } // decodeSveContigFFLoadSS -- 2.30.2