From 77b8fb05b3ae9223abb7bac05d8af6892cfa251a Mon Sep 17 00:00:00 2001 From: Kyrylo Tkachov Date: Fri, 1 Jun 2018 15:50:18 +0000 Subject: [PATCH] [AArch64] Used prefer aliases SXTL(2) and UXTL(2) The SSHL and USHL instructions are used with a shift operand of zero to sign and zero-extend integer vectors into wider modes. GCC makes extensive use of them to "unpack" vectors. AArch64 defines a shorthand alias for that case. Instead of writing: SSHLL ., ., 0 we can write SXTL ., . Similar for the unsigned versions and the high-part versions (SSHL2 -> SXTL2). This makes the assembly of vectorised functions a bit more readable. * config/aarch64/aarch64-simd.md (aarch64_simd_vec_unpack_lo_): Use UXTL and SXTL assembler mnemonics. (aarch64_simd_vec_unpack_hi_): Use UXTL2 and SXTL2 assembler mnemonics. From-SVN: r261073 --- gcc/ChangeLog | 8 ++++++++ gcc/config/aarch64/aarch64-simd.md | 4 ++-- 2 files changed, 10 insertions(+), 2 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 87305aebeeb..24cf22e1bd6 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,11 @@ +2018-06-01 Kyrylo Tkachov + + * config/aarch64/aarch64-simd.md + (aarch64_simd_vec_unpack_lo_): Use UXTL and SXTL assembler + mnemonics. + (aarch64_simd_vec_unpack_hi_): Use UXTL2 and SXTL2 assembler + mnemonics. + 2018-06-01 Richard Sandiford PR tree-optimization/85989 diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index 4e5c42b0f15..dc4e0263096 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -1492,7 +1492,7 @@ (match_operand:VQW 2 "vect_par_cnst_lo_half" "") )))] "TARGET_SIMD" - "shll\t%0., %1., 0" + "xtl\t%0., %1." [(set_attr "type" "neon_shift_imm_long")] ) @@ -1503,7 +1503,7 @@ (match_operand:VQW 2 "vect_par_cnst_hi_half" "") )))] "TARGET_SIMD" - "shll2\t%0., %1., 0" + "xtl2\t%0., %1." [(set_attr "type" "neon_shift_imm_long")] ) -- 2.30.2