From 77c0f9e7ba460d62c921caa5221b6b1fbde0d267 Mon Sep 17 00:00:00 2001 From: =?utf8?q?Nicolai=20H=C3=A4hnle?= Date: Sun, 19 Nov 2017 15:24:28 +0100 Subject: [PATCH] radeonsi/gfx10: initialize GE_{MAX,MIN}_VTX_INDX/INDX_OFFSET Acked-by: Bas Nieuwenhuizen --- src/gallium/drivers/radeonsi/si_state.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c index 4d76e13e527..0044353fd66 100644 --- a/src/gallium/drivers/radeonsi/si_state.c +++ b/src/gallium/drivers/radeonsi/si_state.c @@ -5456,7 +5456,11 @@ static void si_init_config(struct si_context *sctx) si_pm4_set_reg(pm4, R_02800C_DB_RENDER_OVERRIDE, 0); } - if (sctx->chip_class >= GFX9) { + if (sctx->chip_class >= GFX10) { + si_pm4_set_reg(pm4, R_030964_GE_MAX_VTX_INDX, ~0); + si_pm4_set_reg(pm4, R_030924_GE_MIN_VTX_INDX, 0); + si_pm4_set_reg(pm4, R_030928_GE_INDX_OFFSET, 0); + } else if (sctx->chip_class >= GFX9) { si_pm4_set_reg(pm4, R_030920_VGT_MAX_VTX_INDX, ~0); si_pm4_set_reg(pm4, R_030924_VGT_MIN_VTX_INDX, 0); si_pm4_set_reg(pm4, R_030928_VGT_INDX_OFFSET, 0); -- 2.30.2