From 77e7f9b3c17cdc857f9c91e31d366eccde45126f Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Fri, 5 Jul 2019 19:18:52 +0200 Subject: [PATCH] core/spi: make cs_n optional (sometimes managed externally) --- litex/soc/cores/spi.py | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/litex/soc/cores/spi.py b/litex/soc/cores/spi.py index 64c20002..bf12cd15 100644 --- a/litex/soc/cores/spi.py +++ b/litex/soc/cores/spi.py @@ -30,7 +30,8 @@ class SPIMaster(Module, AutoCSR): self._status = CSRStatus(1) self._mosi = CSRStorage(data_width) self._miso = CSRStatus(data_width) - self._cs = CSRStorage(len(pads.cs_n), reset=1) + if hasattr(pads, "cs_n"): + self._cs = CSRStorage(len(pads.cs_n), reset=1) self.irq = Signal() @@ -101,8 +102,9 @@ class SPIMaster(Module, AutoCSR): ) # Chip Select generation ------------------------------------------------------------------- - for i in range(len(pads.cs_n)): - self.comb += pads.cs_n[i].eq(~self._cs.storage[i] | ~cs) + if hasattr(pads, "cs_n"): + for i in range(len(pads.cs_n)): + self.comb += pads.cs_n[i].eq(~self._cs.storage[i] | ~cs) # Master Out Slave In (MOSI) generation (generated on spi_clk falling edge) --------------- mosi_data = Signal(data_width) -- 2.30.2