From 77f3f9bf9eaec6f7095f711024d76a342655863b Mon Sep 17 00:00:00 2001 From: Matthew Wahab Date: Mon, 29 Jun 2015 16:12:12 +0000 Subject: [PATCH] re PR target/65697 (__atomic memory barriers not strong enough for __sync builtins) 2015-06-29 Matthew Wahab PR target/65697 * gcc.target/arm/armv-sync-comp-swap.c: New. * gcc.target/arm/armv-sync-op-acquire.c: New. * gcc.target/arm/armv-sync-op-full.c: New. * gcc.target/arm/armv-sync-op-release.c: New. From-SVN: r225134 --- gcc/ChangeLog | 8 ++++++++ gcc/testsuite/gcc.target/arm/armv8-sync-comp-swap.c | 10 ++++++++++ gcc/testsuite/gcc.target/arm/armv8-sync-op-acquire.c | 10 ++++++++++ gcc/testsuite/gcc.target/arm/armv8-sync-op-full.c | 10 ++++++++++ gcc/testsuite/gcc.target/arm/armv8-sync-op-release.c | 8 ++++++++ 5 files changed, 46 insertions(+) create mode 100644 gcc/testsuite/gcc.target/arm/armv8-sync-comp-swap.c create mode 100644 gcc/testsuite/gcc.target/arm/armv8-sync-op-acquire.c create mode 100644 gcc/testsuite/gcc.target/arm/armv8-sync-op-full.c create mode 100644 gcc/testsuite/gcc.target/arm/armv8-sync-op-release.c diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 6ecc469a814..fd533ab464f 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,11 @@ +2015-06-29 Matthew Wahab + + PR target/65697 + * gcc.target/arm/armv-sync-comp-swap.c: New. + * gcc.target/arm/armv-sync-op-acquire.c: New. + * gcc.target/arm/armv-sync-op-full.c: New. + * gcc.target/arm/armv-sync-op-release.c: New. + 2015-06-29 Matthew Wahab PR target/65697 diff --git a/gcc/testsuite/gcc.target/arm/armv8-sync-comp-swap.c b/gcc/testsuite/gcc.target/arm/armv8-sync-comp-swap.c new file mode 100644 index 00000000000..f96c81a8a9c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/armv8-sync-comp-swap.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { do-require-effective-target arm_arch_v8a_ok } */ +/* { dg-options "-O2" } */ +/* { dg-add-options arm_arch_v8a } */ + +#include "../aarch64/sync-comp-swap.x" + +/* { dg-final { scan-assembler-times "ldrex" 2 } } */ +/* { dg-final { scan-assembler-times "stlex" 2 } } */ +/* { dg-final { scan-assembler-times "dmb" 2 } } */ diff --git a/gcc/testsuite/gcc.target/arm/armv8-sync-op-acquire.c b/gcc/testsuite/gcc.target/arm/armv8-sync-op-acquire.c new file mode 100644 index 00000000000..8d6659b70de --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/armv8-sync-op-acquire.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { do-require-effective-target arm_arch_v8a_ok } */ +/* { dg-options "-O2" } */ +/* { dg-add-options arm_arch_v8a } */ + +#include "../aarch64/sync-op-acquire.x" + +/* { dg-final { scan-assembler-times "ldrex" 1 } } */ +/* { dg-final { scan-assembler-times "stlex" 1 } } */ +/* { dg-final { scan-assembler-times "dmb" 1 } } */ diff --git a/gcc/testsuite/gcc.target/arm/armv8-sync-op-full.c b/gcc/testsuite/gcc.target/arm/armv8-sync-op-full.c new file mode 100644 index 00000000000..a5ad3bd822f --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/armv8-sync-op-full.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { do-require-effective-target arm_arch_v8a_ok } */ +/* { dg-options "-O2" } */ +/* { dg-add-options arm_arch_v8a } */ + +#include "../aarch64/sync-op-full.x" + +/* { dg-final { scan-assembler-times "ldrex" 12 } } */ +/* { dg-final { scan-assembler-times "stlex" 12 } } */ +/* { dg-final { scan-assembler-times "dmb" 12 } } */ diff --git a/gcc/testsuite/gcc.target/arm/armv8-sync-op-release.c b/gcc/testsuite/gcc.target/arm/armv8-sync-op-release.c new file mode 100644 index 00000000000..0d3be7b8c0e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/armv8-sync-op-release.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { do-require-effective-target arm_arch_v8a_ok } */ +/* { dg-options "-O2" } */ +/* { dg-add-options arm_arch_v8a } */ + +#include "../aarch64/sync-op-release.x" + +/* { dg-final { scan-assembler-times "stl" 1 } } */ -- 2.30.2