From 7824c04000ce227a5f97d30004a5b2dd23bc014a Mon Sep 17 00:00:00 2001 From: lkcl Date: Sat, 30 Apr 2022 15:42:59 +0100 Subject: [PATCH] --- openpower/sv/svp64/appendix.mdwn | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/openpower/sv/svp64/appendix.mdwn b/openpower/sv/svp64/appendix.mdwn index 9ec5bed07..2871bd9bc 100644 --- a/openpower/sv/svp64/appendix.mdwn +++ b/openpower/sv/svp64/appendix.mdwn @@ -970,7 +970,12 @@ What, then, of `sv.madded`? If the destination is hard-coded to RT and RT+1 the instruction is not useful when Vectorised because the output will be overwritten on the next element. To solve this is easy: define the destination registers as RT and RT+MAXVL -respectively. +respectively. This makes it easy for compilers to statically allocate +registers even when VL changes dynamically. + +Bear in mind that both RT and RT+MAXVL are starting points for Vectors, +and bear in mind that element-width overrides still have to be taken +into consideration, * [[isa/svfixedarith]] -- 2.30.2