From 7836c85919a289e806c4dbd3e7d080914049b130 Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Thu, 28 Dec 2017 15:42:14 -0800 Subject: [PATCH] broadcom/vc5: Disable early Z when the stencil func isn't ALWAYS. Apparently the other funcs will have observable differences when early Z is enabled. Fixes (new) simulator assertion failures in dEQP-GLES3.functional.rasterizer_discard.basic.clear_depth. --- src/gallium/drivers/vc5/vc5_state.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/gallium/drivers/vc5/vc5_state.c b/src/gallium/drivers/vc5/vc5_state.c index 35d5e1df509..0d6699ae57b 100644 --- a/src/gallium/drivers/vc5/vc5_state.c +++ b/src/gallium/drivers/vc5/vc5_state.c @@ -165,8 +165,10 @@ vc5_create_depth_stencil_alpha_state(struct pipe_context *pctx, cso->depth.func == PIPE_FUNC_LEQUAL) && (!cso->stencil[0].enabled || (cso->stencil[0].zfail_op == PIPE_STENCIL_OP_KEEP && + cso->stencil[0].func == PIPE_FUNC_ALWAYS && (!cso->stencil[1].enabled || - cso->stencil[1].zfail_op == PIPE_STENCIL_OP_KEEP)))); + (cso->stencil[1].zfail_op == PIPE_STENCIL_OP_KEEP && + cso->stencil[1].func == PIPE_FUNC_ALWAYS))))); } const struct pipe_stencil_state *front = &cso->stencil[0]; -- 2.30.2