From 783b23a43811ba30e98c3be126fac19a49d72de2 Mon Sep 17 00:00:00 2001 From: lkcl Date: Fri, 9 Sep 2022 13:43:40 +0100 Subject: [PATCH] --- openpower/sv/rfc/ls001/discussion.mdwn | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/openpower/sv/rfc/ls001/discussion.mdwn b/openpower/sv/rfc/ls001/discussion.mdwn index 10cc182fd..892c28930 100644 --- a/openpower/sv/rfc/ls001/discussion.mdwn +++ b/openpower/sv/rfc/ls001/discussion.mdwn @@ -10,6 +10,19 @@ although the "penalty" is that any such "escape-sequenced" 32-bit instructions require a prefix-marker bit, it does effectively double the **entirety** of the 32-bit Major Opcode space. +Section 1.6.3: + +``` +Prefix bits 6:7 are used to identify one of four prefix for- +mat types. When bit 6 is set to 0 (prefix types 00 and +01), the suffix is not a defined word instruction (i.e., +requires the prefix to identify the alternate opcode +space the suffix is assigned to as well as additional or +extended operand and/or control fields); when bit 6 is +set to 1 (prefix types 10 and 11), the prefix is modifying +the behavior of a defined word instruction in the suffix. +``` + this "doubling" is already public and part of EXT001, the idea here is to mirror that (bit 6), but unlike EXT001, use bit 7 to mark whether the instruction is SVP64-vector or SVP64-single. -- 2.30.2