From 78560aac86b763306798192aa375ed04a5b192a0 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 15 Jul 2019 08:31:26 -0700 Subject: [PATCH] Revert "Fix first divergence in #1178" This reverts commit 1122a2e0671ed00b7c03658f5012e34df12f26de. --- passes/opt/wreduce.cc | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/passes/opt/wreduce.cc b/passes/opt/wreduce.cc index 65068238b..1fbc41082 100644 --- a/passes/opt/wreduce.cc +++ b/passes/opt/wreduce.cc @@ -430,7 +430,6 @@ struct WreduceWorker for (auto w : module->wires()) complete_wires.insert(mi.sigmap(w)); - std::vector> swap_wire_names; for (auto w : module->selected_wires()) { int unused_top_bits = 0; @@ -455,12 +454,9 @@ struct WreduceWorker log("Removed top %d bits (of %d) from wire %s.%s.\n", unused_top_bits, GetSize(w), log_id(module), log_id(w)); Wire *nw = module->addWire(NEW_ID, GetSize(w) - unused_top_bits); module->connect(nw, SigSpec(w).extract(0, GetSize(nw))); - swap_wire_names.emplace_back(w, nw); + module->swap_names(w, nw); } - for (const auto &i : swap_wire_names) - module->swap_names(i.first, i.second); - if (!remove_init_bits.empty()) { for (auto w : module->wires()) { if (w->attributes.count("\\init")) { -- 2.30.2