From 7863611de3305208effe96fbbef5eaf49b60c904 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Tue, 28 Jan 2014 23:15:29 +0000 Subject: [PATCH] r600g: port the layered surface rendering patch from radeonsi This just makes r600 and evergreen do what the radeonsi codepaths do for layered rendering. This makes the 2d amd_vertex_shader_layer test pass on evergreen. Signed-off-by: Dave Airlie Reviewed-by: Alex Deucher --- src/gallium/drivers/r600/evergreen_state.c | 18 ++++++++--------- src/gallium/drivers/r600/r600_state.c | 21 ++++++++++---------- src/gallium/drivers/r600/r600_state_common.c | 1 - 3 files changed, 19 insertions(+), 21 deletions(-) diff --git a/src/gallium/drivers/r600/evergreen_state.c b/src/gallium/drivers/r600/evergreen_state.c index c784f2fe20d..c86e812182b 100644 --- a/src/gallium/drivers/r600/evergreen_state.c +++ b/src/gallium/drivers/r600/evergreen_state.c @@ -1407,7 +1407,7 @@ void evergreen_init_color_surface(struct r600_context *rctx, struct pipe_resource *pipe_tex = surf->base.texture; unsigned level = surf->base.u.tex.level; unsigned pitch, slice; - unsigned color_info, color_attrib, color_dim = 0; + unsigned color_info, color_attrib, color_dim = 0, color_view; unsigned format, swap, ntype, endian; uint64_t offset, base_offset; unsigned non_disp_tiling, macro_aspect, tile_split, bankh, bankw, fmask_bankh, nbanks; @@ -1416,10 +1416,15 @@ void evergreen_init_color_surface(struct r600_context *rctx, bool blend_clamp = 0, blend_bypass = 0; offset = rtex->surface.level[level].offset; - if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) { + if (rtex->surface.level[level].mode == RADEON_SURF_MODE_LINEAR) { + assert(surf->base.u.tex.first_layer == surf->base.u.tex.last_layer); offset += rtex->surface.level[level].slice_size * surf->base.u.tex.first_layer; - } + color_view = 0; + } else + color_view = S_028C6C_SLICE_START(surf->base.u.tex.first_layer) | + S_028C6C_SLICE_MAX(surf->base.u.tex.last_layer); + pitch = (rtex->surface.level[level].nblk_x) / 8 - 1; slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64; if (slice) { @@ -1569,12 +1574,7 @@ void evergreen_init_color_surface(struct r600_context *rctx, surf->cb_color_info = color_info; surf->cb_color_pitch = S_028C64_PITCH_TILE_MAX(pitch); surf->cb_color_slice = S_028C68_SLICE_TILE_MAX(slice); - if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) { - surf->cb_color_view = 0; - } else { - surf->cb_color_view = S_028C6C_SLICE_START(surf->base.u.tex.first_layer) | - S_028C6C_SLICE_MAX(surf->base.u.tex.last_layer); - } + surf->cb_color_view = color_view; surf->cb_color_attrib = color_attrib; if (rtex->fmask.size) { surf->cb_color_fmask = (base_offset + rtex->fmask.offset) >> 8; diff --git a/src/gallium/drivers/r600/r600_state.c b/src/gallium/drivers/r600/r600_state.c index 98e69247bf0..e0c801e60ed 100644 --- a/src/gallium/drivers/r600/r600_state.c +++ b/src/gallium/drivers/r600/r600_state.c @@ -1264,6 +1264,7 @@ static void r600_init_color_surface(struct r600_context *rctx, unsigned level = surf->base.u.tex.level; unsigned pitch, slice; unsigned color_info; + unsigned color_view; unsigned format, swap, ntype, endian; unsigned offset; const struct util_format_description *desc; @@ -1277,10 +1278,15 @@ static void r600_init_color_surface(struct r600_context *rctx, } offset = rtex->surface.level[level].offset; - if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) { + if (rtex->surface.level[level].mode == RADEON_SURF_MODE_LINEAR) { + assert(surf->base.u.tex.first_layer == surf->base.u.tex.last_layer); offset += rtex->surface.level[level].slice_size * - surf->base.u.tex.first_layer; - } + surf->base.u.tex.first_layer; + color_view = 0; + } else + color_view = S_028080_SLICE_START(surf->base.u.tex.first_layer) | + S_028080_SLICE_MAX(surf->base.u.tex.last_layer); + pitch = rtex->surface.level[level].nblk_x / 8 - 1; slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64; if (slice) { @@ -1466,14 +1472,7 @@ static void r600_init_color_surface(struct r600_context *rctx, } surf->cb_color_info = color_info; - - if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) { - surf->cb_color_view = 0; - } else { - surf->cb_color_view = S_028080_SLICE_START(surf->base.u.tex.first_layer) | - S_028080_SLICE_MAX(surf->base.u.tex.last_layer); - } - + surf->cb_color_view = color_view; surf->color_initialized = true; } diff --git a/src/gallium/drivers/r600/r600_state_common.c b/src/gallium/drivers/r600/r600_state_common.c index 0c32974430f..f237d26c376 100644 --- a/src/gallium/drivers/r600/r600_state_common.c +++ b/src/gallium/drivers/r600/r600_state_common.c @@ -1724,7 +1724,6 @@ struct pipe_surface *r600_create_surface_custom(struct pipe_context *pipe, assert(templ->u.tex.first_layer <= util_max_layer(texture, templ->u.tex.level)); assert(templ->u.tex.last_layer <= util_max_layer(texture, templ->u.tex.level)); - assert(templ->u.tex.first_layer == templ->u.tex.last_layer); if (surface == NULL) return NULL; pipe_reference_init(&surface->base.reference, 1); -- 2.30.2